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2010-08-13CPU: Tidy up endianness handling for mmapped "IPR"s.Gabe Black
2010-07-22Power: The condition register should be set or cleared upon a system callTimothy M. Jones
return to indicate success or failure.
2010-07-22LSQ Unit: After deleting part of a split request, set it to NULL so that itTimothy M. Jones
isn't accidentally deleted again later (causing a segmentation fault).
2010-07-22Port: Only indicate that a SimpleTimingPort is drained if its send event isTimothy M. Jones
not scheduled, as well as the transmit list being empty.
2010-07-22O3CPU: Fix a bug where stores in the cpu where never marked as split.Timothy M. Jones
2010-07-22Syscall: Don't close the simulator's standard file descriptors.Timothy M. Jones
2010-07-22O3CPU: O3's tick event gets squashed when it is switched out. When repeatedlyTimothy M. Jones
switching between O3 and another CPU, O3's tick event might still be scheduled in the event queue (as squashed). Therefore, check for a squashed tick event as well as a non-scheduled event when taking over from another CPU and deal with it accordingly.
2010-07-22Power: Provide a utility function to copy registers from one thread contextTimothy M. Jones
to another in the Power ISA.
2010-07-21stats: unify the two stats distribution type betterNathan Binkert
2010-07-21stats: cleanup a few small problems in statsNathan Binkert
2010-07-21python: add a sorted dictionary classNathan Binkert
It would be nice if python had a tree class that would do this for real, but since we don't, we'll just keep a sorted list of keys and update it on demand.
2010-07-21python: Add mechanism to override code compiled into the exectuableNathan Binkert
If the user sets the environment variable M5_OVERRIDE_PY_SOURCE to True, then imports that would normally find python code compiled into the executable will instead first check in the absolute location where the code was found during the build of the executable. This only works for files in the src (or extras) directories, not automatically generated files. This is a developer feature!
2010-07-21Fix x86 XCHG macro-op to use locked micro-ops for all memory accessesTushar Krishna
2010-07-17SimObject: transparently forward Python attribute refs to C++.Steve Reinhardt
This tidbit was pulled from a larger patch for Tim's sake, so the comment reflects functions that haven't been exported yet. I hope to commit them soon so it didn't seem worth cleaning up.
2010-07-15ARM: Make an SRS instruction with a bad mode cause an undefined instruction ↵Gabe Black
fault.
2010-07-13ARM: Adjust the FP_Base_DepTag to be larger than the largest int reg index.Gabe Black
2010-07-08cache: fix bug in SC upgrade handlingSteve Reinhardt
This bug was introduced with the recent rework of SC failure handling in cset f97b62be544f.
2010-07-08garnet: Added topology print function to Garnet printStatsBrad Beckmann
2010-07-08NetworkMessage copy constructor fixTushar Krishna
2010-07-05checkpointing: another small overload fixSteve Reinhardt
On Nate's advice, overload 'char' as well as 'signed char' and 'unsigned char'.
2010-07-05sim: allow SimObject subclasses to define classmethodsSteve Reinhardt
(without requiring a leading underscore) Also a little cleanup on type names in SimObject.py.
2010-07-05sim: fold StartupCallback into SimObjectSteve Reinhardt
There used to be a reason to have StartupCallback be a separate object, but not any more. Now it's just confusing.
2010-07-05checkpointing: minor cleanup.Steve Reinhardt
Move some static checkpoint stuff into the Checkpoint object namespace.
2010-07-05checkpointing: fix minor bugSteve Reinhardt
Somehow we now need to explicitly specialize on 'signed char' and not just 'char' to catch cases like int8_t
2010-07-05process: get rid of some unused code & varsSteve Reinhardt
2010-07-05process: minor format/style cleanupSteve Reinhardt
2010-06-22style: updated garnet to match M5 coding styleTushar Krishna
2010-06-28inorder: remove another debug statKorey Sewell
2010-06-26inorder: remove debugging statKorey Sewell
m5 doesnt do stats specific to binary and this resource request stat is probably only useful for people who really know the ins/outs of the model anyway
2010-06-25inorder: Return Address Stack bugKorey Sewell
the nextPC was getting sent to the branch predictor not the current PC, so the RAS was returning the wrong PC and mispredicting everything.
2010-06-25inorder: resource scheduling backendKorey Sewell
replace priority queue with vector of lists(1 list per stage) and place inside a class so that we have more control of when an instruction uses a particular schedule entry ... also, this is the 1st step toward making the InOrderCPU fully parameterizable. See the wiki for details on this process
2010-06-25X86: Fix div2 flag calculation.Gabe Black
2010-06-24inorder: cleanup virtual functionsKorey Sewell
remove the annotation 'virtual' from function declaration that isnt being derived from
2010-06-24inorder: enforce 78-character ruleKorey Sewell
2010-06-24inorder: exe_unit_stats for resolved branchesKorey Sewell
2010-06-23inorder: squash from memory stallKorey Sewell
this applies to multithreading models which would like to squash a thread on memory stall
2010-06-23inorder: record load/store trace dataKorey Sewell
2010-06-23inorder: update branch predictorKorey Sewell
- use InOrderBPred instead of Resource for DPRINTFs - account for DELAY SLOT in updating RAS and in squashing - don't let squashed instructions update the predictor - the BTB needs to use the ASID not the TID to work for multithreaded programs - add stats for BTB hits
2010-06-23inorder-stats: add instruction type statsKorey Sewell
also, remove inst-req stats as default.good for debugging but in terms of pure processor stats they aren't useful
2010-06-23inorder: stall signal handlingKorey Sewell
remove stall only when necessary add debugging printfs
2010-06-23inorder: tick schedulingKorey Sewell
use nextCycle to calculate ticks after addition
2010-06-22cache: fix longstanding prefetcher bugSteve Reinhardt
Thanks to Joe Gross for pointing this out (again?). Apologies to anyone who pointed it out earlier and we didn't listen.
2010-06-23O3ThreadContext: When taking over from a previous context, only assert thatTimothy M. Jones
the system pointers match in Full System mode.
2010-06-16cache: fail store conditionals when upgrade loses raceSteve Reinhardt
Requires new "SCUpgradeReq" message that marks upgrades for store conditionals, so downstream caches can fail these when they run into invalidations. See http://www.m5sim.org/flyspray/task/197
2010-06-16cache: fix dirty bit settingSteve Reinhardt
Only set the dirty bit when we actually write to a block (not if we thought we might but didn't, as in a failed SC or CAS). This requires makeing sure the dirty bit stays set when we get an exclusive (writable) copy in a cache-to-cache transfer from another owner, which n turn requires copying the mem-inhibit flag from timing-mode requests to their associated responses.
2010-06-15stats: rename print to display in the mysql code too...sorryNathan Binkert
2010-06-15stats: rename print to display so it work in pythonNathan Binkert
2010-06-15stats: only consider a formula initialized if there is a formulaNathan Binkert
2010-06-14stats: get rid of the never-really-used event stuffNathan Binkert
2010-06-14util: clean up attrdict and import multiattrdict into m5.utilNathan Binkert