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2007-03-07Move the magic m5 PageTableFault into sim/faults.[hh,cc] since it's the same ↵Gabe Black
across all architectures. --HG-- extra : convert_revision : 18d441eb7ac44df4df41771bfe3dec69f7fa70ec
2007-03-07Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem --HG-- extra : convert_revision : d764fe37c71269a04fcede6cbf30e24262447e89
2007-03-07Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/tmp/newmem --HG-- extra : convert_revision : f078a05729b5fe464a06a58bc4adcb374f560572
2007-03-07*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscRegAli Saidi
--HG-- extra : convert_revision : f799b65f1b2a6bf43605e6870b0f39b473dc492b
2007-03-07Add setData functions for the new Twin??_t types.Gabe Black
--HG-- extra : convert_revision : 6f4e08e76eb4a95eb08b11632f6e33ba458723b6
2007-03-07Add some constructors and an output operator to the Twin??_t types so that ↵Gabe Black
o3 SPARC will compile again. --HG-- extra : convert_revision : af987aaeac87ee92a3b55cf0839d994cf7dea1af
2007-03-07Make byteswap work correctly on Twin??_t types.Gabe Black
--HG-- extra : convert_revision : a8a14078d62c24e480ffa69591edfc775d1d76cc
2007-03-06CleanupNathan Binkert
--HG-- extra : convert_revision : 31f1b0f760a6eb861652440f9d42aaf123ef4833
2007-03-06Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86 --HG-- extra : convert_revision : 0822fbcc377781b53d2de9ba40ab9d985ccbc039
2007-03-06Python parameters types need analogous C++ typesNathan Binkert
--HG-- extra : convert_revision : d068dfec69b28d48fc299a4108e165decfaaace7
2007-03-06Move all of the parameters of the Root SimObject so they areNathan Binkert
directly configured by python. Move stuff from root.(cc|hh) to core.(cc|hh) since it really belogs there now. In the process, simplify how ticks are used in the python code. --HG-- extra : convert_revision : cf82ee1ea20f9343924f30bacc2a38d4edee8df3
2007-03-06Get X86 to load an elf and start a process for it.Gabe Black
src/arch/x86/SConscript: Add in process source files. src/arch/x86/isa_traits.hh: Replace magic constant numbers with the x86 register names. src/arch/x86/miscregfile.cc: Make clear the miscreg file succeed. There aren't any misc regs, so clearing them is very easy. src/arch/x86/process.hh: An X86 process class. src/base/loader/elf_object.cc: Add in code to recognize x86 as an architecture. src/base/traceflags.py: Add an x86 traceflag src/sim/process.cc: Add in code to create an x86 process. src/arch/x86/intregs.hh: A file which declares names for the integer register indices. src/arch/x86/linux/linux.cc: src/arch/x86/linux/linux.hh: A very simple translation of SPARC's linux.cc and linux.hh. It's probably not correct for x86, but it might not be correct for SPARC either. src/arch/x86/linux/process.cc: src/arch/x86/linux/process.hh: An x86 linux process. The syscall table is split out into it's own file. src/arch/x86/linux/syscalls.cc: The x86 Linux syscall table and the uname function. src/arch/x86/process.cc: The x86 process base class. tests/test-progs/hello/bin/x86/linux/hello: An x86 hello world test binary. --HG-- extra : convert_revision : f22919e010c07aeaf5757dca054d9877a537fd08
2007-03-05Python atexit handlers are called in reverse order.Nathan Binkert
Fix things so the stats dump happens last. --HG-- extra : convert_revision : ea842dbcbb77dd1c715c4e5b57d2470e558c4265
2007-03-05Fill out a stub version of the vtophys header file.Gabe Black
--HG-- extra : convert_revision : 2c10a80a2f73207539e3f98b4a3b864d431f5035
2007-03-05Add in NumGDBRegs so the constructor to the base class can get all it's ↵Gabe Black
arguments. --HG-- extra : convert_revision : fcec1ad134b53a419a952e556ed75cb1559a1127
2007-03-05Reorganize the floating point register file a little.Gabe Black
--HG-- extra : convert_revision : 643c147b77e931d49ac559681d4bbda737f6e1c7
2007-03-05Add some new source files.Gabe Black
--HG-- extra : convert_revision : 94f3f19eb91b7f54918640b7605008eb1fe75fc7
2007-03-05Stub decoder. This is probably even farther from finished than it looks...Gabe Black
--HG-- extra : convert_revision : a39a158fec4560f6eb7a6987592c473677c0b1ba
2007-03-05Add stub for x86 process creationGabe Black
--HG-- extra : convert_revision : 3bdbc415a73c6bb4d723f68714a96c9f922ba5e6
2007-03-05Add x86 version of call to "decode"Gabe Black
--HG-- extra : convert_revision : bb799dcea58b51d6e1d3d744581ea48c5c1490fe
2007-03-05Add x86 to the Arch enum in the object file class.Gabe Black
--HG-- extra : convert_revision : bc8c5e78aac0e9033d6cbc756d8092369ac29072
2007-03-05Added missing include.Gabe Black
--HG-- extra : convert_revision : 9d00209e5c0ae8aa5ac37f9558627ee212a72c9b
2007-03-05Added LargestRead type for x86. I might have picked the wrong type.Gabe Black
--HG-- extra : convert_revision : 5570a595b9adbe9c35f9b4f8dd3b50533b5beb97
2007-03-05Stub implementation for x86.Gabe Black
--HG-- extra : convert_revision : 3eccbf699bb62139a06a9b249e56bd205bc316ed
2007-03-05Stub implementation for x86Gabe Black
--HG-- extra : convert_revision : dd6b4d14070a2e99c179c5f780c9935847da8eda
2007-03-05Added fault generation functions. I would still like to see these go away. ↵Gabe Black
The page table fault should be moved into sim/faults.hh because it's a "fake" m5 fault for se mode and shouldn't vary between architectures. --HG-- extra : convert_revision : cafe25befd64f83a424c1a09f5e62a16df5408ad
2007-03-05Added an x86 dyninstGabe Black
--HG-- extra : convert_revision : 2317e9bb0bcf8010ab5d02019f7a14eeb7b1459c
2007-03-05Added stub implementations or prototypes for all the functions in this file.Gabe Black
--HG-- extra : convert_revision : c0170eae8aeae130f81618ae49a60f879c2b523f
2007-03-05Added in a missing include.Gabe Black
--HG-- extra : convert_revision : 712480fef36bf7a34c2c0b8d19dd82689eb78a1d
2007-03-05Filled in a stub header file for setting the result of a syscall.Gabe Black
--HG-- extra : convert_revision : f0a2cdf7d669834b90444fc390b0aceede474737
2007-03-05Filled in a stub header file for a stacktrace object. I'm still not sure ↵Gabe Black
what this is for, and it probably doesn't work on anything but Alpha. --HG-- extra : convert_revision : 9bc3833628d31799a7b578c450dac096a19aead3
2007-03-05Filled in a stub header file for remote gdbGabe Black
--HG-- extra : convert_revision : 6289181697142f672548a4d4cf6e010171cb98e1
2007-03-05Correct a typoGabe Black
--HG-- extra : convert_revision : 1e8ef87ddb28873045a08bd104afc8ce129c4299
2007-03-05Make the constructor (and all the other functions) publicGabe Black
--HG-- extra : convert_revision : 9d572651fc1722b15ae7dbc59c108d680c911f04
2007-03-05Various touch upsGabe Black
--HG-- extra : convert_revision : 19ff30d969a46adbd256f674582a9e7d398b56ed
2007-03-05Added a missing include.Gabe Black
--HG-- extra : convert_revision : 15a1b49ff9e0a1a15bd2500bec9ec9bc95ee5898
2007-03-05Added a missing include.Gabe Black
--HG-- extra : convert_revision : 62583e5a5647913fb36e1aae265e8ac52a165829
2007-03-05Fix up the remote gdb include gaurds so it doesn't use the same symbol as ↵Gabe Black
Alpha does. --HG-- extra : convert_revision : b75dbdd95ceb4ec71275588a5cf8e6b614cf4539
2007-03-05x86 register file includes.Gabe Black
--HG-- extra : convert_revision : c00a077dd7ae8f6b48c6939034be244bcf48d715
2007-03-05Include the x86 specific traits file.Gabe Black
--HG-- extra : convert_revision : bcf448aedd832022527cc972f7a1f0433987c564
2007-03-05Stub x86 Fault class which just panics.Gabe Black
--HG-- extra : convert_revision : abfcf4005ec636b1e6c085515b63c1d8e69e3370
2007-03-05A new file for x86 specific parameters. This could be implemented as a sim ↵Gabe Black
object? --HG-- extra : convert_revision : 51757435bb0b20132f3ec5782db31382bb2cca18
2007-03-05Add in a declaration of class Checkpoint rather than expecting it to come ↵Gabe Black
from some other include. --HG-- extra : convert_revision : adbd4899508e3d30959a504a48402f01d1187099
2007-03-05Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86 --HG-- extra : convert_revision : b585cea2221377eb2fceea8976c46a17c0034f51
2007-03-04Don't use the exact same name as a system header #defineNathan Binkert
--HG-- extra : convert_revision : 099e380395fc1fdaef993b019d3d4e596e8076c2
2007-03-03add a sparc fs regressionAli Saidi
src/dev/sparc/iob.cc: don't warn on cpu restart/idle/halt stuff tests/SConscript: add sparc target in test Sconscript util/regress: Add SPARC_FS target in regress --HG-- extra : convert_revision : 37fa21700ec4c350d87ca9723bc3359feb81c50a
2007-03-03Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : fd6464c9883783c7c2cbefba317f4a0f20dd24cb
2007-03-03Add Iob and remove the fake deviceAli Saidi
configs/common/FSConfig.py: add an attachOnChipIO to force people to think about where "onchip" i/o should be connected in their hierarchy --HG-- extra : convert_revision : cf79a9a00760b7daf28063f407a04bd38b956843
2007-03-03Implement Niagara I/O interface and rework interruptsAli Saidi
configs/common/FSConfig.py: Use binaries we've compiled instead of the ones that come with Legion src/arch/alpha/interrupts.hh: get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number src/arch/sparc/asi.cc: Add AsiIsInterrupt() to AsiIsMmu() src/arch/sparc/faults.cc: src/arch/sparc/faults.hh: Add InterruptVector type src/arch/sparc/interrupts.hh: rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared src/arch/sparc/isa_traits.hh: Add the "interrupt" trap types to isa traits src/arch/sparc/miscregfile.cc: add names for all the misc registers and possible post an interrupt when TL is changed. src/arch/sparc/miscregfile.hh: Add a helper function to post an interrupt when pil < some set softint src/arch/sparc/regfile.cc: src/arch/sparc/regfile.hh: InterruptLevel shouldn't really live here, moved to interrupt.hh src/arch/sparc/tlb.cc: Add interrupt ASIs to TLB src/arch/sparc/ua2005.cc: Add checkSoftInt to check if a softint needs to be posted Check that a tickCompare isn't scheduled before scheduling one Post and clear interrupts on queue writes and what not src/base/bitfield.hh: Add an helper function to return the msb that is set src/cpu/base.cc: src/cpu/base.hh: get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending src/cpu/intr_control.cc: src/cpu/intr_control.hh: src/dev/alpha/tsunami_cchip.cc: src/python/m5/objects/IntrControl.py: Make IntrControl have a system pointer rather than using a cpu pointer to get one src/dev/sparc/SConscript: add iob to SConsscrip tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out: update config.ini/out for intrcntrl not having a cpu pointer anymore --HG-- extra : convert_revision : 38614f6b9ffc8f3c93949a94ff04b7d2987168dd
2007-03-03include signal.hNathan Binkert
--HG-- extra : convert_revision : 9b5ad2704dfd63a1aa8ad0e4275fd0e3a7d32d6d
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-18 08:30:32 +0000