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Age
Commit message (
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Author
2012-03-09
O3/Ozone: Eliminate dead code counting software prefetch insts
Geoffrey Blake
2012-03-09
CheckerCPU: Add function stubs to non-ARM ISA source to compile with CheckerCPU
Geoffrey Blake
2012-03-09
CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable
Geoffrey Blake
2012-03-09
ARM: Don't reset CPUs that are going to be switched in.
Ali Saidi
2012-03-09
System: Move code in initState() back into constructor whenever possible.
Ali Saidi
2012-03-09
ARM: Fix valgrind reported error on O3 that was causing minor stats changes.
Ali Saidi
2012-03-09
cache: Allow main memory to be at disjoint address ranges.
Ali Saidi
2012-03-06
build scripts: Made minor modifications to reduce build overhead time.
Marc Orr
2012-03-02
DynInst: get rid of dead MyHash code.
Steve Reinhardt
2012-03-02
CPU: Check that the interrupt controller is created when needed
Andreas Hansson
2012-03-02
Ruby: Rename RubyPort::sendTiming to avoid overriding base class
Andreas Hansson
2012-03-02
ARM: FIx a bug preventing multiple cores booting a VExpress_EMM machine.
Ali Saidi
2012-03-01
ARM: FIx missing cf controller connection.
Ali Saidi
2012-03-01
VNC: spacing
Chander Sudanthi
2012-03-01
ARM: Add support for Versatile Express extended memory map
Ali Saidi
2012-03-01
ARM: Add RTC device for ARM platforms.
Ali Saidi
2012-03-01
ARM: Add limited CP14 support.
Matt Horsnell
2012-03-01
Cache: Fix an issue with LRU when bonus block is used to complete transaction.
Ali Saidi
2012-03-01
ARM: move kernel func event to correct location.
Dam Sunwoo
2012-03-01
ARM: fix bits-to-fp conversion function declarations.
Giacomo Gabrielli
2012-03-01
x86: Fix x86 TLB and Walker
Nilay Vaish
2012-03-01
x86: Fix switching of CPUs
Nilay Vaish
2012-02-29
MEM: Make all the port proxy members const
Andreas Hansson
2012-02-29
SWIG: Ensure ptrdiff_t is a known type in gcc >= 4.6.1
Andreas Hansson
2012-02-26
X86: Use the M5PanicFault fault in execute methods instead of calling panic.
Gabe Black
2012-02-24
MEM: Simplify cache ports preparing for master/slave split
Andreas Hansson
2012-02-24
MEM: Prepare mport for master/slave split
Andreas Hansson
2012-02-24
Ruby: Simplify tester ports by not using SimpleTimingPort
Andreas Hansson
2012-02-24
MEM: Move all read/write blob functions from Port to PortProxy
Andreas Hansson
2012-02-24
MEM: Make port proxies use references rather than pointers
Andreas Hansson
2012-02-24
MEM: Move port creation to the memory object(s) construction
Andreas Hansson
2012-02-24
CPU: Round-two unifying instr/data CPU ports across models
Andreas Hansson
2012-02-24
MEM: Fatal when no port can be found for an address
Andreas Hansson
2012-02-20
SimObject: make get_config_as_dict() tolerate undefined params
Steve Reinhardt
2012-02-14
MEM: Fix residual bus ports and make them master/slave
Andreas Hansson
2012-02-13
BPred: Fix RAS to handle predicated call/return instructions.
Mrinmoy Ghosh
2012-02-13
BP: Fix several Branch Predictor issues.
Mrinmoy Ghosh
2012-02-13
MEM: Explicit ports and Python binding on CopyEngine
Andreas Hansson
2012-02-13
MEM: Pass the ports from Python to C++ using the Swig params
Andreas Hansson
2012-02-13
MEM: Introduce the master/slave port roles in the Python classes
Andreas Hansson
2012-02-12
X86: open flags: Another patch from Vince Weaver
Gabe Black
2012-02-12
cpu: add separate stats for insts/ops both globally and per cpu model
Anthony Gutierrez
2012-02-12
mem: fix cache stats to use request ids correctly
Dam Sunwoo
2012-02-12
mem: Add a master ID to each request object.
Ali Saidi
2012-02-12
prefetcher: Make prefetcher a sim object instead of it being a parameter on c...
Mrinmoy Ghosh
2012-02-11
SPARC: Make PSTATE and HPSTATE a BitUnion.
Gabe Black
2012-02-10
Ruby: Remove isTagPresent() calls from Sequencer.cc
Nilay Vaish
2012-02-10
MESI: Add queues for stalled requests
Nilay Vaish
2012-02-10
sim/system: initialize the pagePtr variable
Nilay Vaish
2012-02-10
O3 CPU: Improve handling of delayed commit flag
Nilay Vaish
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