Age | Commit message (Collapse) | Author |
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into zower.eecs.umich.edu:/eecshome/m5/newmem
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extra : convert_revision : 74b2352b8f088e38cd1ecf3a8233b45df0476d93
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into zower.eecs.umich.edu:/home/gblack/m5/newmemmemops
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extra : convert_revision : c49b760eac758dbde30867cb638fcb3b790f4721
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configs/common/FSConfig.py:
Make a SPARC system create an IO bus.
src/python/m5/objects/T1000.py:
Create a T1000 platform
src/arch/sparc/miscregfile.cc:
Initialize the strand status register to the value legion provides.
src/cpu/exetrace.cc:
Truncate an ExtMachInst to a MachInst before comparing with Legion.
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extra : convert_revision : e4189b572a5297e8362f5bd26d87b74736c8e5f1
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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extra : convert_revision : 8d61b474428d494b1a5382e4cf95934ad54e35dd
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src/cpu/simple/timing.cc:
Various updates for deleting requests more properly.
The major change is moving the deletion of the fetch request/packet to after the instruction has executed and completed. This should fix a few bugs because Ron's memory system didn't expect a call for a functional access while a timing access was being processed.
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extra : convert_revision : c7cf114bb1ff3cdaa7b0a40ed4c5302dc9d3a522
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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extra : convert_revision : b216fcdb2632dce68ac18932b0c13408eb1aeaf4
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src/mem/bus.cc:
Make it so that invalidates being sent from the responder up don't call the responder
but they should also not Panic.
src/mem/packet.hh:
If we don't have data in the packet, don't call deleteData:
Example: InvalidateRequests never have data.
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extra : convert_revision : 18766bc9f3bb4d852ac651d094254d347abd1634
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into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops
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extra : convert_revision : 966246877ac1f1e6c2675d413b0b405cccfecbeb
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into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem
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extra : convert_revision : 8e805b9bbd5c64c2e5951384b3c6ef712062d08c
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extra : convert_revision : 7e27b23b66c743b4625a1dd9d8d6ba61bff45168
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into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
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extra : convert_revision : 6abd919711966eaaa157483557a3f953b02dde01
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make a likewise updateIntrInfo for Sparc that's blank so it doesn't fart on build
src/arch/sparc/interrupts.hh:
make a likewise updateIntrInfo for Sparc that's blank so it doesn't fart on build
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extra : convert_revision : 5f469d0cf897479b42703104cd801a8ef923fcae
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extra : convert_revision : 566d73438efb87ca683e4dee23454d880db3dfc7
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into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem
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extra : convert_revision : cda58e6e63f2f909b85a510fb76d35d49d8042b9
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extra : convert_revision : 0be66513cb0cff07c0c2b50c97c1ea74d52b0dc9
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extra : convert_revision : 7bdf68f445b79b1b5dbcdfa5fa1005c68d03724c
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into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem
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extra : convert_revision : 753831a9f6f79d07e6ee122ab894e24161d2e722
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extra : convert_revision : cd2eb8c00adcb34b8693a4d1a66187927c0f6803
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src/mem/bridge.cc:
Update brdiges, now that snoop addresses are properly forwarded.
Bus bridge should only handle snoops on the second phase (SNOOP_COMMIT)
src/mem/bus.cc:
src/mem/bus.hh:
Make sure if a busBridge has access to both things that snoop and things that respond it only takes the request once
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extra : convert_revision : 26cc9ee4429be45d4476fa435e0e9a54843c2509
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extra : convert_revision : 7f082ba5c1cd2445aec731950c31a877aac23a75
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sendTiming has not returned in the call stack.
src/mem/cache/base_cache.cc:
Sometimes a functional access comes while waiting on a outstanding packet being sent.
This could be because Timing CPU does some post processing on the recvTiming which send functional access.
Either the CPU should leave the pkt/req around (so They can be referenced in the mem system). Or the mem
system should remove them from outstanding lists and reinsert them if they fail in the sendTiming.
I did the later, eventually we should consider doing the former if that is the correct behavior.
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extra : convert_revision : be41e0d2632369dca9d7c15e96e5576d7583fe6a
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extra : convert_revision : 736372131b046eccf3520292fb3c086dc568d918
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src/mem/bus.cc:
Only call snoop once per port, need to fix it so snoop ranges that overlap aren't added to list
Functional accesses that call snoop and it goes to a higher bus may change the src, reset it after each snoop.
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extra : convert_revision : 7276059c798a85cb9d138ccc5531298ecd055c13
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src/mem/bus.cc:
Actually return the snoop list when asked for it.
Don't get stuck in infinite functional loops
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extra : convert_revision : 8e6dafbd10b30d48d28b6b5d4b464e8e8f6a3ddc
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src/cpu/simple/atomic.cc:
Make the atomic cpu return 0 on snoops.
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extra : convert_revision : aad96ad36e0c764c7cfef8b0c8e97877574f5845
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extra : convert_revision : 82882eb131aa66eba9f281b64db21d5cbfefb1b9
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extra : convert_revision : 717b62510f28a69af99453309fbbb458359eeb2a
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the Debug param context
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extra : convert_revision : 40e9dcfa9faedbe0c90a43f908f20a7c14ded6a4
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into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix
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extra : convert_revision : 6ef2249bfa3f7149830efdb42a313422090da7d7
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extra : convert_revision : 40dfbb72c4e418c54e909c54dad5fe6ef7017cb4
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into vm1.(none):/home/stever/bk/newmem-head
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extra : convert_revision : faab7569deefde94c20133b2f70a8567bcaa2960
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extra : convert_revision : 746bdf92334d220158eb0eb6bf113b4dcedbb354
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extra : convert_revision : 05db10e20d33302fe830d5759b8881b1233aca87
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src/cpu/o3/fetch_impl.hh:
Fetch needs to make sure it isn't waiting on an Icache access.
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extra : convert_revision : b53eb58b9e5a00bdb394134586d1f84f84d1c6e1
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into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops
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extra : convert_revision : eed3b6a650635d43fe75c2158c8417647af640d9
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into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix
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extra : convert_revision : b98236507bb8996ce605b48b5a5a6a7aac297dc5
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extra : convert_revision : 661b412b0ae670181b89cb7dbc5e9d813804aa7a
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Rename cc_main to internal.main
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extra : convert_revision : e938005f600fbf8a43435e29426a948f4501f072
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src/arch/alpha/interrupts.hh:
No need for this now that the ThreadContext is being used to set these IPRs in interrupts.
Also split up the interrupt checking from the updating of the IPL and interrupt summary.
src/arch/alpha/tlb.cc:
Check the PC for whether or not it's in PAL mode, not the addr.
src/cpu/o3/alpha/cpu.hh:
Split up getting the interrupt from actually processing the interrupt.
src/cpu/o3/alpha/cpu_impl.hh:
Splut up the processing of interrupts.
src/cpu/o3/commit_impl.hh:
Update for ISA-oriented interrupt changes.
src/cpu/o3/fetch_impl.hh:
Fix broken if statement from PcPAL updates, and properly populate the request fields.
Also more debugging output.
src/cpu/ozone/cpu_impl.hh:
Updates for ISA-oriented interrupt stuff.
src/cpu/ozone/front_end_impl.hh:
Populate request fields properly.
src/cpu/simple/base.cc:
Update for interrupt stuff.
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extra : convert_revision : 9bac3f9ffed4948ee788699b2fa8419bc1ca647c
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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extra : convert_revision : 498304c24435437f8f1942bb8aeafe69ba22a089
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check here for responses that match as well
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extra : convert_revision : 69c3628a381a9da885fab0272abf40c3411a5f0f
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Fixes for Mem Leak associated with Writebacks.
src/mem/cache/miss/mshr_queue.cc:
Fixes for Mem Leak associated with Writebacks. (Double Delete removed)
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extra : convert_revision : 7a52ddd57da35995896f2c4438a58aa53f762416
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If you get inserted in the front, reschedule the event
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extra : convert_revision : eccbacf5ec85600e5b68eb554fee2c0e2b65e965
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extra : convert_revision : cfdd5b6911422fbb733677c43d027aa4407fbc85
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src/mem/cache/cache_impl.hh:
When upgrades change to readEx make sure to allocate the block
Fix dprintf
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extra : convert_revision : 8700a7e47ad042c8708302620b907849c4bfdded
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src/mem/cache/base_cache.cc:
On a delayed response, be sure to call the fixPacket wrapper to toggle hasData flag.
src/mem/packet.cc:
src/mem/packet.hh:
Create a wrapper to toggle the hasData flag on delayed responses
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extra : convert_revision : 1ced8d4e3dc12a059fb7636d59e429cd3dd46901
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extra : convert_revision : 4f5b610f364876b29ad0e04f1757e4b42d1f2bd8
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