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The ISA parser used to generate different copies of exec functions
for each exec context class a particular CPU wanted to use. That's
since been changed so that those functions take a pointer to the base
ExecContext, so the code which would generate those extra functions
can be removed, and some functions which used to be templated on an
ExecContext subclass can be untemplated, or minimally less templated.
Now that some functions aren't going to be instantiated multiple times
with different signatures, there are also opportunities to collapse
templates and make many instruction definitions simpler within the
parser. Since those changes will be less mechanical, they're left for
later changes and will probably be done in smaller increments.
Change-Id: I0015307bb02dfb9c60380b56d2a820f12169ebea
Reviewed-on: https://gem5-review.googlesource.com/5381
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The fixed image writer (which was dumping .bmp images only) has been
replaced by the configurable one in HDLcd device. Default format is
Auto, which gives gem5 the freedom to choose the format it prefers.
Change-Id: I0643266556bb10b43cdebd628f6daa2cd5e105dd
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5183
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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This commit modifies the default behaviour of the vnc frame dumping
process: rather than using 'Bitmap' as a default parameter value, it is
using 'Auto'. Auto parameter is letting gem5 to choose the most
efficient image format among the available ones.
Change-Id: I3c8e2b5a34a5925d24892880ac362dfe38de36e3
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5182
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Originally it was possible to use a Bitmap writer class for dumping a
framebuffer snapshot in a .bmp file. This patch enables you to choose
another format. In particular it implements the writing of PNG Images
using libpng library. The latter has to be already installed in your
machine, otherwise gem5 will default to the Bitmap format. This
configurable writer has been introduced in the VNC frame dumping mechanism,
which is storing changed frame buffers from the VNC server
Change-Id: Id7e5763c82235f1ce90381c8486b85a7cce734ce
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5181
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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When decoding VEX prefixed instructions, the x86 predecoder wasn't walking
past the opcode byte and so was also interpreting it as the modRM byte.
Reported-by: likunxi@fas.harvard.edu
Change-Id: I6d4bdabfa03411704c48d905c50c7b23072fc615
Reviewed-on: https://gem5-review.googlesource.com/5281
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
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Despite online documentation, the type used for sin_addr.s_addr is not
actually an unsigned long, it is an in_addr_t. When an unsigned long is a 64
bit value, the endian conversion moves the relevant bits of the 32 bit
in_addr_t to positions which are truncated away. This forces the value to 0
which means to bind to any interface, the opposite of the intended effect.
Change-Id: I53c63dea6bd88144dfef1a9a49b478fab30a8ba2
Reviewed-on: https://gem5-review.googlesource.com/5301
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The high speed bit-reversing function is now used
for the Aarch64/32 RBIT instruction implementation.
Change-Id: Id5a8a93d928d00fd33ec4061fbb586b8420a1c1b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5262
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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This patch introduces a high-speed template function for mirroring the
bits (MSB=>LSB) in a variable length word. The function is achieving
high performances since it is using a look-up table.
Change-Id: Ib0d0480e68d902f25655f74d243de305103eff75
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5261
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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std::make_unique is not available for C++11 compilers, and it has been
introduced only in C++14. Since gem5 is not officially supporting the
latter at the moment, this patch allows to use it in gem5 if including
base/compiler.hh. If compiled under C++14, std::make_unique will be
used instead.
Change-Id: Ibf1897fad0a1eb1cb0c683cc25170feaa6841997
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5201
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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Fixes compile error for gem5.fast on CLANG due to unused variable.
Change-Id: Iabe777a27d75ee8bfa7b214fff577aed3c7582c7
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/4980
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
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A recent scons cleanup introduced a small bug when setting the variant path of
the regression test SConscript. When turned into a relative path, the
directory can be interpreted differently depending on what it's considered
relative to. When left as a scons node, there is no ambiguity.
Change-Id: I162afdc4fcef81db096ec8304f81bc98fa6bf899
Reviewed-on: https://gem5-review.googlesource.com/5221
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
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Generating dependency/build product information in the isa parser breaks scons
idea of how a build is supposed to work. Arm twisting it into working forced
a lot of false dependencies which slowed down the build.
Change-Id: Iadee8c930fd7c80136d200d69870df7672a6b3ca
Reviewed-on: https://gem5-review.googlesource.com/5081
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
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Change-Id: Ided438af19c9b8504d4624119c4d9fb5157c7cf0
Reviewed-on: https://gem5-review.googlesource.com/4720
Reviewed-by: Paul Rosenfeld <prosenfeld@micron.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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When a store exclusive is executed, whether it is successful or not,
the exclusives monitor is cleared and therefore we need to signal an
event for the PE.
Change-Id: I383c88c769c0ac5f5d36c4b5d39c9681134d3a20
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4480
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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ARM systems require the coordination of the global and local
monitors. When the system is run without caches the global monitor is
implemented in the abstract memory object. This change adds a callback
from the abstract memory that notifies the local monitor when the
global monitor is cleared.
Additionally, for ARM systems the local monitor signals the event
register and wakes the thread context up. Subsequent wait-for-event
(WFE) instructions will be immediately signaled.
Change-Id: If6c038f3a6bea7239ba4258f07f39c7f9a30500b
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3760
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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The size of the store entry in the LSQ is used to indicate a fault in
the execution of the store. At the same time, a store that is
predicated false will also have 0 size in the corresponding store
queue entry. This changeset ensures that we check if the store was
predicated false before checking the size field. This way we avoid
printing stores as faulting when they are only predicated false.
Change-Id: Ie07982197bd73d7b44d26a3257d54ecb103a952a
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4821
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The O3CPU allows stores to commit before they are completed and as
soon as they enter the store queue. This is the reason why stores are
verified by the the checker CPU, separately, once they complete
and after they are sent to the memory.
Store conditionals, on the other hand, have an additional writeback
stage in the pipeline as they return their result to a register,
similarly to loads. This is the reason why they do not commit
before they receive a response from the memory. This allows store
conditionals to be verified by the checker CPU as soon as they
commit in the same way as all other non-store insturctions.
At the same time, the presense of a checker CPU should not require
changes to way we handle instructions. This change removes explicit
calls to:
* incorrectly set the extra data of the request to 0 (a subsequent
call to completeAcc already does this without making any ISA
assumptions about the return value of the failed store conditional)
* complete failing store conditionals
Change-Id: If21d70b21caa55b35e9fdcc50f254c590465d3c3
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4820
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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mremapFunc(...) did not respect Process::mmapGrowsDown(). This resulted
in an attempt to remap into an already allocated region and a panic in
FuncPageTable::allocate(...). This behavior can be observed in
435.gromacs.
Change-Id: Ib3ad33816126c76506d69679bdcefa7a98ef69f9
Reviewed-on: https://gem5-review.googlesource.com/4700
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
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MOV Rd,Cd is MR encoded but the control register is operand 2
not operand 1 hence this needs to be MODRM_REG not MODRM_RM.
While MOV Cd,Rd is RM encoded registers are also swapped, so
it also needs to be MODRM_REG as well (as it already correctly is).
This fixes incorrect UD2 reportings leading to invalid traps
reported in O3 on X86 FS introduced with 4e939a7 .
Change-Id: Ib33c8ba87b00e0264d33da44fff64ed9e4d2d9d8
Reviewed-on: https://gem5-review.googlesource.com/4861
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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Make the traceData panic for Vectors a warn_once. It's a pity it's
not implemented but it's not a reason to abort the simulation entirely.
Change-Id: I5e97258fd4e3fa385cfe0c4b400524d1f7b154df
Reviewed-on: https://gem5-review.googlesource.com/4860
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
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FreeBSD before the early 11 development is expecting a char *
for stack.ss_sp rather than the standards compliant void *.
Catch that case and allow gem5 to compile on old FreeBSD versions.
Change-Id: Ic0ae560b52bfe5b3905ae87df791d349e053ec97
Reviewed-on: https://gem5-review.googlesource.com/4660
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Also centralize the code which iterates over the parameters of a simnode's
children, and remove a copy/paste block of code in the DVFS block of code.
Change-Id: I01305fbff59346010780ee386ba97ad9106b1f5d
Reviewed-on: https://gem5-review.googlesource.com/4849
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
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Only panic if there are disks which would actually be connected to it beyond
its limit. Also skip past disks which are set to NULL. This is useful since
it lets you set up disks on different ports of the controller instead of
filling them contiguously.
Change-Id: I92f1316d3ad6931e25bfffeb34fb2603c0b95ce7
Reviewed-on: https://gem5-review.googlesource.com/4848
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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Change-Id: I1ba6f6b196b7dfa790d1baaa23640bb3ed73f450
Reviewed-on: https://gem5-review.googlesource.com/4847
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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Change-Id: Ibdc48af8e5a461077f75d781cfd8191586c54115
Reviewed-on: https://gem5-review.googlesource.com/4846
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
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The name is 'Null', and is what __str__ returns.
Change-Id: I113f52496f5e9133b8d03206289b719fda003582
Reviewed-on: https://gem5-review.googlesource.com/4845
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
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Null simobjects don't have any descendants.
Change-Id: Ia43a99056709f422c9c817c017912d23d689fb1e
Reviewed-on: https://gem5-review.googlesource.com/4844
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
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Change-Id: I3842176f147997105fcc62aaf9cb93b9896708be
Reviewed-on: https://gem5-review.googlesource.com/4843
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
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The existing code was essentially doing the same thing, but in a more
roundabout and obscure way. One difference between the two versions is that
I believe this will stop as soon as it encounters an element without a
parent, where the original version would call has_parent() on all the
elements regardless.
Change-Id: Ia1fef3083fc88fca11f8ecfca453476e33194695
Reviewed-on: https://gem5-review.googlesource.com/4842
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
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NullSimObject doesn't have a has_parent function, and it's not clear what its
return value should be if one were added. The appropriate value seems to
depend on why some other bit of code is checking if there's a parent in the
first place.
In SimObjectVector, the has_parent function is checking whether all of its
elements have a parent. In this particular case, the most reasonable thing
to do seems to be to just skip those elements.
Change-Id: I5f8cad66d1b22c5e37962492fd77cff9371e5af8
Reviewed-on: https://gem5-review.googlesource.com/4841
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
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This lets attempts to set_parent on NullSimObject fall away harmlessly
without having to add a bunch of checks whenever set_parent is called.
Change-Id: I6d3510772ba71e765c4739e486e9f3d2460c4e11
Reviewed-on: https://gem5-review.googlesource.com/4840
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
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This will let somebody consuming the memory packet trace make sense out of
the master IDs passed along with individual accesses.
Change-Id: I621d915f218728066ce95e6fc81f36d14ae7e597
Reviewed-on: https://gem5-review.googlesource.com/4800
Reviewed-by: Rahul Thakur <rjthakur@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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This map is intended to map from request MasterIDs to master names. It could
be used to map to arbitrary strings in other situations, however.
The original idea to store this information was to add a new message type
which would store one ID and the string associated with it. This change stores
the IDs in the header instead so that they'll be easy to find and all
available before the packet data.
One downside of this approach is that it won't be possible to add new master
ID strings as they come up during a trace. If that becomes an issue, the two
approaches could be combined and messages could be added which would augment
the map in the header.
Also worth mentioning is that the proto2 version of the protobuf description
language does not support the "map" field type, and the protoc compiler on my
workstation doesn't support proto3. Because that's such an appropriate
representation for this data, the map is represented in an equivalent format
described in the proto3 documentation.
Change-Id: I137c8611c33d9ce6589e196d50c8638c1d88750c
Reviewed-on: https://gem5-review.googlesource.com/4782
Reviewed-by: Rahul Thakur <rjthakur@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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There's a spot for it in the packet trace protobuf, so we should fill it
with something.
Change-Id: I784feb3f668e1b20d67b6ef98d012bcf59b7bd40
Reviewed-on: https://soc-sim-internal-review.googlesource.com/3483
Reviewed-by: Rahul Thakur <rjthakur@google.com>
Reviewed-on: https://gem5-review.googlesource.com/4781
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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That can be recorded in a packet trace.
Change-Id: I3813ab4ea5aadeb40b355ff01f10e8ecab2bb790
Reviewed-on: https://soc-sim-internal-review.googlesource.com/3482
Reviewed-by: Rahul Thakur <rjthakur@google.com>
Reviewed-on: https://gem5-review.googlesource.com/4780
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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* When dispatching multiple gem5 simulations at once, they race
for the socket id, resulting in a panic when calling 'bind'. To
avoid this problem, the socket id is now created before the diod
process is created. In case of a race, a panic is called in the
gem5 process, whereas before the panic was called in the diod
process where it didn't have any effect.
* In some cases killing the diod process in terminateDiod() using
only SIGTERM failed, so a call using SIGKILL is added.
Change-Id: Ie10741e10af52c8d255210cd4bfe0e5d761485d3
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2821
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The primary difference between loadState and unserialize, at least when
eventually using the default SimObject implementation of loadState, is that
unserialize is called only if there's a corresponding section in the
checkpoint being restored. In this particular case, the AlphaProcess class
calls the generic Process unserialize function, and that does other critical
initialization like set up the processes page table. If the unserialize
function isn't called, other serious problems would break the simulation
anyway.
This removes the final custom implementation of loadState.
Change-Id: If50062392196bd37efd5ba04fd7aee6907b00dc6
Reviewed-on: https://gem5-review.googlesource.com/4741
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The primary difference between using loadState and letting the default
implementation of loadState call unserialize is that whether or not that code
is called is dependent on that object being associated with a section in the
checkpoint file being unserialized. Since there's always a "root" object,
there should always be a section for it in the checkpoint and those should be
equivalent.
This removes one custom implementation of the loadState function.
Change-Id: Ia674ccc18e141f38746e22ccfddc21475b1a0731
Reviewed-on: https://gem5-review.googlesource.com/4740
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The MuxingKvmGic class defined a few functions related to checkpointing which
did nothing other than call the underlying Pl390 implementation. These are
unnecessary in general, and are particularly unnecessary for the loadState
function which is a very lightly used part of the checkpointing interface.
It's not actually defined in Pl390 either, and falls through to the
underlying implementation.
Change-Id: I84aae13d4966df0f4fdd1a72aee0bf1af01392ff
Reviewed-on: https://gem5-review.googlesource.com/4760
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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This stat is only incremented by Alpha. Also move the _hwrei into the Alpha
stats object since it's the class that actually sets up and maintains that
value and it probably should have been there all along.
Change-Id: Ibd038a33230c01432c160490926d8e1e55f8ccb0
Reviewed-on: https://gem5-review.googlesource.com/4601
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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The kernel stat mechanism should really be refactored and moved somewhere
else, but in the mean time there's some old cruft that can be cleared away.
Change-Id: I21e725de590dda0d20bf3bc675bbe976c7b1bd86
Reviewed-on: https://gem5-review.googlesource.com/4600
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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When different sizes were set for the choice and global saturation
counter (e.g. ex5_big), the threshold calculation used the wrong
size. Thus the branch predictor always predicted "not taken" for
choice > global.
Change-Id: I076549ff1482e2280cef24a0d16b7bb2122d4110
Reviewed-on: https://gem5-review.googlesource.com/4560
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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Coverage was wrongly set to PartialAddrRangeCoverage in the case of
disjoint adjacent ranges
Change-Id: I29aaf5145e6cdcf5f0b8f4e009d57ee57bd4c944
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/4640
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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When writing a bitmask of counters to PMSWINC, the PMU currently
increments the corresponding counters regardless of what they are
configured to count. According to the ARM ARM (D5.10.4), counters
should only be updated if they have been configured to count
software events (event type 0).
Change-Id: I5b2bc1fae55faa342b863721c9838342442831a9
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4285
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Change-Id: I94a4bf4a633aeed550f8c01ccae824add3b85eb0
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4284
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
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Change-Id: Ie5ef1aaaef46cf8ef8fa4b0fc8f7efb8cde9b489
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4283
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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Recent gcc versions complain about a missing VecDisabled not having an
explicit FaultVals instantiation.
Change-Id: I439e7b3a7d5cad20590f52b3f374ead3f3f070a6
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4282
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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Change-Id: I3a52fcdb449c7df1612466270aa2c9b0a0f3afef
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4281
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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PyBind normally casts integers returned from the C to long in
Python. This is normally fine since long in most cases behaves just
like an int. However, when passing the return value from getcode() to
sys.exit, unexpected behavior ensues. Due to the way the function is
defined, any type other than int (with the exception of None) will be
treated as an error and be equivalent to sys.exit(1).
Since we frequently use the sys.exit(event.getCode()) pattern, we need
to ensure that the function returns an integer. This change adds an
explicit type conversion to a Python integer in the wrapper code.
Change-Id: I73d6b881025064afa2b2e6eb4512fa2a4b0a87da
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jose Marinho <jose.marinho@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4280
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Joe Gross <joe.gross@amd.com>
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When a split load hits a memory region where IPRs are mapped, the
Writebackevent which is scheduled for that was carrying a data packet
that was not correctly initialized which caused an assertion to fire
when the Writeback event is processed.
Change-Id: I71a4e291f0086f7468d7e8124a0a8f098088972f
Signed-off-by: Matthias Hille <matthiashille8@gmail.com>
Reported-by: Matthias Hille <matthiashille8@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/4620
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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