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2018-09-20systemc: Don't schedule the update phase if the event queue is null.Gabe Black
That happens when an update is requested before the initialization phase has started. In that case, the update phase will be manually run and no event needs to be scheduled, even if that was possible. Change-Id: I2008e29064d282f82bd1935dbe5b94407aa925b0 Reviewed-on: https://gem5-review.googlesource.com/12078 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-20systemc: Use an std::list to track all modules.Gabe Black
This is less efficient when modules are destroyed since the list isn't sorted, and each module needs to find its own entry to remove. The benefit is that entries added to the end of the list while the list is being iterated over will still be included, and that the order the modules are added will be preserved so that it matches what the order in the regression tests. Change-Id: I5af5d15f316fa58561e8fd9ca77f667ddc8b2c5e Reviewed-on: https://gem5-review.googlesource.com/12077 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-20systemc: Track the module in the end_of_elaboration callback.Gabe Black
sc_objects constructed during that callback are considered children of the module the callback belongs to. Change-Id: I164863a10beef6d0e2c6d9c5e8f2642d80769dca Reviewed-on: https://gem5-review.googlesource.com/12076 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-20systemc: Partially implement the sc_signal class template.Gabe Black
There are a few details of this class that still need to be fleshed out, but this implements most of it. Change-Id: I6f8b546aacd8537d4341dc91e59b95864ae0f7c4 Reviewed-on: https://gem5-review.googlesource.com/12075 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-20systemc: Add a nonstandard sc_status pretty printer operator.Gabe Black
This operator exists in the Accellera implementation, and is necessary to make the test output match. Change-Id: I266629d6c936d4846e88e35af36555fb392b181c Reviewed-on: https://gem5-review.googlesource.com/12074 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-20systemc: Set the scheduler's event queue earlier.Gabe Black
The kernel can set the event queue during its own construction which will ensure that the scheduler can schedule events as early as possible. Change-Id: I0e47ca0a667e77d36c97860cd7c6b7577415c801 Reviewed-on: https://gem5-review.googlesource.com/12073 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-20systemc: "Implement" sc_interface's methods.Gabe Black
Most don't do anything. Make default_event() return a dummy event to avoid dereferencing a null pointer. Change-Id: I8d6d576d3a1f585029c387cd414bbebf2d670644 Reviewed-on: https://gem5-review.googlesource.com/12072 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-20systemc: Implement a few more member functions for sc_time.Gabe Black
Change-Id: I40a7fb278f2a0ec4124589e02e4441c1866c86ea Reviewed-on: https://gem5-review.googlesource.com/12071 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-20systemc: Use the new python interface to delay fixing the timescale.Gabe Black
This is necessary if an sc_time object is constructed globally, either directly or indirectly, before python is available to fix the timescale. The call will be deferred until the interpretter is up and ready. Change-Id: I486c0a90d44a0e0f0ad8c530b7148e1cff04a5cc Reviewed-on: https://gem5-review.googlesource.com/12070 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-20systemc: Generalize working with the systemc python module from C++.Gabe Black
This change pulls the systemc python module creation code out of sc_main and puts it into a more general purpose python.hh and python.cc which can be used by other code to add other entries into that module without having to track that in a central place. This change also adds a mechanism for notifying C++ code that the embedded python interpretter is up and ready to interact with in case it needs to call some python only functionality. An example of that is the code which tracks and then fixes the timescale for the simulator. Change-Id: I9afcd5a089b21d23ebc1b5fdb6f643ae2f7e5f11 Reviewed-on: https://gem5-review.googlesource.com/12069 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-20systemc: Ignore a warning in the reference test outputs.Gabe Black
The warning is about deprecated sc_module constructors which don't take an sc_module_name. Change-Id: I2ef864a5bdac93eb8104a842179ffe45a8335085 Reviewed-on: https://gem5-review.googlesource.com/12068 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-20systemc: Fix the seed used with sc_gen_unique_name for sc_port.Gabe Black
The seed should only be "port" not "sc_port". Change-Id: Ia046103abc0a9ed283fcb7cf7d8069383a1e2b0d Reviewed-on: https://gem5-review.googlesource.com/12067 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-20systemc: Implement sc_gen_unique_name.Gabe Black
The Accellera implementation statically allocates the buffer it uses to build the unique names and only allocates the name generator if it's going to be used for a particular module. I assume that's to avoid allocating a large buffer if it's not going to be used. In this implementation, I use an std::string which manages its own memory and so shouldn't need to be selectively allocated. I also use a string stream to construct the name instead of sprintf. Change-Id: If92c68586a85b5d27c067a75a6e9ebbf00d8c785 Reviewed-on: https://gem5-review.googlesource.com/12066 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-20systemc: Always set USE_SYSTEMC=1 when compiling with verify.py.Gabe Black
It doesn't make sense not to have systemc enabled when building the systemc regression tests. Change-Id: I23b81fd4d7cbd0dbf5efbea773d816296d6492be Reviewed-on: https://gem5-review.googlesource.com/12065 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-20systemc: Make verify.py ignore an Info: message.Gabe Black
This message is about how to disable a warning about sc_bit being deprecated. Change-Id: I1a0b12e2ca5b58328e37605ba3f7e3e1a384e351 Reviewed-on: https://gem5-review.googlesource.com/12064 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-20systemc: Adjust a warning to match Accellera.Gabe Black
This is to pass fix a diff in the regression tests. Change-Id: Id1b963df647224d7a3589febe7986353a4a8e440 Reviewed-on: https://gem5-review.googlesource.com/12063 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-19syscall_emul: implement dir-related syscallsBrandon Potter
Add getdents, rmdir, chdir, and mknod to SE mode for x86. Change-Id: I387ea3066869e8999bc0064f74070f4e47c1e9a1 Reviewed-on: https://gem5-review.googlesource.com/12112 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-09-19syscall_emul: refactor FDEntry and children classesBrandon Potter
Strips off superfluous inline specifiers in header file. Changes return types and parameters that deal with strings to include the const& specifiers. Change-Id: I570b1801abb059b91216f0223458d00963b9ca1c Reviewed-on: https://gem5-review.googlesource.com/12111 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-09-19syscall_emul: style changes and FDArray refactorBrandon Potter
Some members were defined as public when they should have been privately declared so these were moved to the appropriate spot. The operator[] had inline specified for for an in-class definition which is redundant since inline definitions are always implicitly inline. Private members had the leading underscore applied to them to denote that they're private (consistent with style guide). Changed static const defined class variable into a constexpr with brace-list initialization. Change-Id: If3054416b57827d1542e9ebab428d67d0e767723 Reviewed-on: https://gem5-review.googlesource.com/12110 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-09-19syscall_emul: expand AuxVector classBrandon Potter
The AuxVector class is responsible for holding Process data. The data that it holds is normally setup by an OS kernel in the process address space. The purpose behind doing this is to pass in information that the process will need for various reasons. (Check out the enum in the header file for an idea of what the AuxVector holds.) The AuxVector struct was changed into a class and encapsulation methods were added to protect access to the member variables. The host ISA may have a different endianness than the simulated ISA. Since data is passed between the process address space and the simulator for auxiliary vectors, we need to worry about maintaining endianness for the right context. Change-Id: I32c5ac4b679559886e1efeb4b5483b92dfc94af9 Reviewed-on: https://gem5-review.googlesource.com/12109 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-09-19mem-cache: Fix non-bijective function in Skewed cachesDaniel R. Carvalho
The hash() function must be bijective for the skewed caches to work, however when the hashing is done on top of a one-bit address, the MSB and LSB refer to the same bit, and therefore their xor will always be zero. This patch adds a fatal error to not allow the user to set an invalid value for the number of sets that would generate that bug. As a side note, the missing header for the bitfields functions has been added. Change-Id: I35a03ac5fdc4debb091f7f2db5db33568d0b0021 Reviewed-on: https://gem5-review.googlesource.com/12724 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-09-18dev, arm: fix error class-memaccess with GCC >= 8.1Maurice Becker
From GCC 8.1 on GCC issues a warning when using memset et al on structs and classes. With the way gem5 builds, this actually prevents successful builds. Instead of using a pointer with SCSIReply as type, we cast to a void pointer to avoid the message. On the way we wrap the memset call into a method of SCSIReply called reset for better code readability. Signed-off-by: Maurice Becker <madnaurice@googlemail.com> Change-Id: I3ed3fd9714be5d253aba01ca00b1863e1ae5cb68 Reviewed-on: https://gem5-review.googlesource.com/12685 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-09-18Pl011: Added registers UART_RSR/UART_ECRMaurice Becker
UART_RSR shows errors with the transmission and UART_ECR can clear those (according to PL011 Technical Reference Manual Revision r1p4). As these transmission errors never occur, they are implemented as RAZ/WI. Both registers exist at the same offset 0x004. RSR is read-only, ECR is write-only. Signed-off-by: Maurice Becker <madnaurice@googlemail.com> Change-Id: Ia9d13c90c65feccf3ecec36a782170755b1e1c02 Reviewed-on: https://gem5-review.googlesource.com/12686 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-17mem: Implement QoS Proportional Fair policyGiacomo Travaglini
Providing a configurable fair scheduling policy based on utilization; utilization is directly proportional to a score which is inversely proportional to the QoS priority. It is meant to avoid starvation of low priority packets. Users can tune the policy by adjusting the weight parameter (weight of the following formula) new_score = ((1.0 - weight) * old_score) + (weight * served_bytes) Change-Id: I7679e234b916c57ebed06cec0ff3cff3cf2aef22 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12359 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-09-14power: Add a clock_period variable to power expressionsSherif Elhabbal
Currently 'Clock period in ticks' stat is not accessible in power equations . This patch adds a variable 'clock_period' to be referenced to get the Clock period in ticks Signed-off-by: Sherif Elhabbal <elhabbalsherif@gmail.com> Change-Id: Icac6a2e2003ed75d1680180e53343b0203139d72 Reviewed-on: https://gem5-review.googlesource.com/12664 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-13Fix SConstruct for asan buildEarl Ou
Sometimes it's easier to debug gem5 built with ASan enabled. This CL fixes some build error when using --with-asan. Bug: None Test: ./scripts/build_gem5 --with-asan --with-ubsan build/ARM/gem5.debug Change-Id: Iaaaaebc3f25749e11f97bf454ddd0153b3de56e7 Reviewed-on: https://gem5-review.googlesource.com/12511 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-09-13arch-arm: Correction for address size in EL1&0 translationAnouk Van Laer
When doing EL0/1 translation in stage2, the physical address size will be defined by the hypervisor (via VTCR_EL2.ps, not TCR.ips). See D10.2.121 of the ARM ARM. Change-Id: Ic7df97c0f5950a648f7408cde3955a640b562c1d Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12552 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-09-13arch-arm: Correction to address size in EL2/EL3Anouk Van Laer
This commit corrects how the address size is determined in EL2/EL3. Previously, TCR_ELx.ips was used but this should be TCR_ELx.ps. Change-Id: I7e5a2f376335532a1d1c8c74d12a416617474ae2 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12551 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-09-13mem-cache: Fix bug in handleAtomicReqMissNikos Nikoleris
"4976ff5 mem-cache: Refactor the recvAtomic function" introduced a bug where if an atomic request that fills in using the tempBlock it will not evict it when it finishes handling the request as it should. This triggers an assertion. This change fixes this bug. Change-Id: I73c808a7e15237eddb36b5448ef6728f7bcf7fd9 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12644 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-09-12dev-arm: fix build to missing Pl390 to Gicv2 renameCiro Santilli
Change-Id: I6756f2c789aaca410d201aa64147443b66afee39 Reviewed-on: https://gem5-review.googlesource.com/12645 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-12config, dev-arm: Fix UART handling baremetal modeCiro Santilli
fs.py in baremetal mode currently fails for the VExpress_GEM5_V1 platform due to inconsistent UART naming with error message: AttributeError: object 'VExpress_GEM5_V1' has no attribute 'uart' Consistently name keep all UARTs in the Arm platforms in a vector named 'uart' or as a single device named 'uart'. Update the configuration scripts to reflect the fact that 'uart' can be a vector. Change-Id: I20b8dbac794d6a9be19b6ce8c335a097872132fb Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12473 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-12dev-arm: rename Pl390 to GicV2Ciro Santilli
The Pl390 model has evolved and acquired a lot of the features from GICv2, which means that the name is no longer appropriate. Rename it to GICv2 since this is more representative of the supported features. GICv2 is backwards compatible with the older Pl390, so we decided to simply rename the class to represent both GICv2 and older interfaces such as the instead of creating a new separate one. Change-Id: I1c05fba8b3cb5841c66480e9f05b8c873eba3229 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12492 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-12dev-arm: improve Pl390 parametersCiro Santilli
Remove default dist_addr and cpu_addr register addresses since those are purely platform specific. Parametrize the cpu_size parameter. RealViewPBX has the Gic CPU and distributor base too close for the newer CPU size of 0x2000, leading to overlap. This was introduced in I90a9f669a46a37d79c6cc542087cf91f2044f104 and makes using RealViewPBX fail with: fatal: system.membus has two ports responding within range [0x1f000100 : 0x1f0020ff]: system.realview.gic.pio system.realview.gic.pio Change-Id: Ic6c0e6b3d4705ff369eb739d54a1173a47819b7d Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12491 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-12cpu: Replace the fastmem with a new CPU modelAndreas Sandberg
The AtomicSimpleCPU used to be able to access memory directly to speed up simulation if no caches are used. This is fine as long as no switching between CPU models is required. In order to switch to a new CPU model that requires caches, we currently need to checkpoint the system and restore it into a new configuration. The new 'atomic_noncaching' memory mode provides a solution that avoids this issue since caches are bypassed in this mode. This changeset removes the old fastmem option from the AtomicSimpleCPU and introduces a new CPU, NonCachingSimpleCPU, which derives from the AtomicSimpleCPU. The NonCachingSimpleCPU uses the same mechanism as the AtomicSimpleCPU used to use when accessing memory in when fastmem was enabled. This changeset also introduces a new switcheroo test that tests switching between a NonCachingSimpleCPU and a TimingSimpleCPU with caches. Change-Id: If01893f9b37528b14f530c11ce6f53c097582c21 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12419 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-09-11systemc: Adjust some whitespace in a print out.Gabe Black
This makes a test output file diff successfully. Change-Id: Ia269b4b33f719a2559197d9296f9acc601ec65f7 Reviewed-on: https://gem5-review.googlesource.com/12062 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Make verify.py ignore another warning.Gabe Black
Also make warning filters more general and easier to add by writing a function to generate them. Change-Id: I8d813ded9ad8a9ccac4e48e5ea80a3c9c23959da Reviewed-on: https://gem5-review.googlesource.com/12061 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Make verify.py compare non output log reference files.Gabe Black
There are only a few of these which are vcd files. If there are reference files which aren't the log and which aren't in the gem5 output directory, mark those tests as failed as well. Change-Id: I2c880c13d0f90ccf16ac0439dbac68de9223cc90 Reviewed-on: https://gem5-review.googlesource.com/12060 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Delete empty/misnamed test reference file.Gabe Black
The name of the reference file doesn't match the name of the test, and is empty. There's also a correctly named log file in the same directory which will be used instead. Change-Id: I6501b465b99af403ae4af6d43189280c4b45fc8f Reviewed-on: https://gem5-review.googlesource.com/12059 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Remove some junk test reference files.Gabe Black
These files have truncated names, and are identical to correct versions of the log files. Change-Id: I1e5e3c8c489d41dea21f62b4664b05bf6a742117 Reviewed-on: https://gem5-review.googlesource.com/12058 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Ensure the terminated event is notified in all cases.Gabe Black
The terminated event was being notified if a process was killed, but not if it was terminated in other ways. This change moves the notification into the helper which sets termination related state. Change-Id: I10aa5ad25875db992c8408dc60f087efc76b336b Reviewed-on: https://gem5-review.googlesource.com/12057 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Make verify.py delete obsolete diff files.Gabe Black
If diff file exists but the underlying diff has been fixed, delete the diff file. Change-Id: Icadc21a61c084198a8a246ab6d00a9b885647cde Reviewed-on: https://gem5-review.googlesource.com/12056 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Make verify.py ignore a warning.Gabe Black
Change-Id: Ia887b7195d84d0ba9e77370d7b928e201ca78731 Reviewed-on: https://gem5-review.googlesource.com/12055 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Teach verify.py to diff files when checking test results.Gabe Black
Currently it just diffs the stdout and ignores other reference files. It also doesn't filter out noise in the diffs from non test related simulator messages. These include startup messages, messages when the simulator finishes executing, and some non-standard warnings, etc. Change-Id: Idcb19edd893cd8818423c2c5ebb6cbfb278baffa Reviewed-on: https://gem5-review.googlesource.com/12054 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Add return code verification to verify.py.Gabe Black
This just checks whether gem5 exited of its own accord with a successful error code, or in other words that it didn't hang or crash. More checking will need to be added to verify the output against the golden reference. Change-Id: I1ddef56aa73b5f700743830bd6212804531c484f Reviewed-on: https://gem5-review.googlesource.com/12053 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Record the test's return code in the output directory.Gabe Black
verify.py will be able to use that value later to determine whether a test was successful. Change-Id: Ib499a4b6f202ee46e66e5de1b61a7e6309df9886 Reviewed-on: https://gem5-review.googlesource.com/12052 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Extend the execute phase of verify.py.Gabe Black
Add -j and --timeout options to the execute phase of verify.py. The --timeout option is implemented using the timeout utility program which is assumed to be available on the host system. Python 3.3 added a timeout argument to the subprocess module which is an alternative approach, but then we would be dependent on python 3.3. -j is implemented using the standard multiprocess.pool.ThreadPool class. Change-Id: I15b92f2b14de6710e2027a6a19984b2644b2a8df Reviewed-on: https://gem5-review.googlesource.com/12051 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Detect a process control corner case and report an error.Gabe Black
This error reporting results in an exception being thrown, and one (or more) of the tests depend on that behavior. Change-Id: I858aa14fbb80b0648392179a6a8d2055c91aedf8 Reviewed-on: https://gem5-review.googlesource.com/12050 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Adjust process status tracking to improve kill/reset support.Gabe Black
This change rearranges how process status is tracked so that the kill and reset mechanisms work in more circumstances and more like they're supposed to according to the spec. This makes another test or two pass. Change-Id: Ie2a683a796155a82092109d5bb45f07c84e06c76 Reviewed-on: https://gem5-review.googlesource.com/12049 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Implement most of the sc_report_handler mechanism.Gabe Black
This doesn't include support for the deprecated integer message ids. Change-Id: I309d58df1cdc464428189eb0b7180edf41ca4f67 Reviewed-on: https://gem5-review.googlesource.com/12048 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-11systemc: Ignore direct requests to mark a process as ready.Gabe Black
That might happen when a process is being marked as ready at the start of simulation. Because the process might not end up on the ready list, displacing it from the init list, excplicitly pop it off the init list as well. Change-Id: Iebf972e3e1baedec17b9b99b4da9dd44cd8e6957 Reviewed-on: https://gem5-review.googlesource.com/12047 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-11 09:14:24 +0000