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AgeCommit message (Expand)Author
2012-03-01ARM: FIx missing cf controller connection.Ali Saidi
2012-03-01VNC: spacingChander Sudanthi
2012-03-01ARM: Add support for Versatile Express extended memory mapAli Saidi
2012-03-01ARM: Add RTC device for ARM platforms.Ali Saidi
2012-03-01ARM: Add limited CP14 support.Matt Horsnell
2012-03-01Cache: Fix an issue with LRU when bonus block is used to complete transaction.Ali Saidi
2012-03-01ARM: move kernel func event to correct location.Dam Sunwoo
2012-03-01ARM: fix bits-to-fp conversion function declarations.Giacomo Gabrielli
2012-03-01x86: Fix x86 TLB and WalkerNilay Vaish
2012-03-01x86: Fix switching of CPUsNilay Vaish
2012-02-29MEM: Make all the port proxy members constAndreas Hansson
2012-02-29SWIG: Ensure ptrdiff_t is a known type in gcc >= 4.6.1Andreas Hansson
2012-02-26X86: Use the M5PanicFault fault in execute methods instead of calling panic.Gabe Black
2012-02-24MEM: Simplify cache ports preparing for master/slave splitAndreas Hansson
2012-02-24MEM: Prepare mport for master/slave splitAndreas Hansson
2012-02-24Ruby: Simplify tester ports by not using SimpleTimingPortAndreas Hansson
2012-02-24MEM: Move all read/write blob functions from Port to PortProxyAndreas Hansson
2012-02-24MEM: Make port proxies use references rather than pointersAndreas Hansson
2012-02-24MEM: Move port creation to the memory object(s) constructionAndreas Hansson
2012-02-24CPU: Round-two unifying instr/data CPU ports across modelsAndreas Hansson
2012-02-24MEM: Fatal when no port can be found for an addressAndreas Hansson
2012-02-20SimObject: make get_config_as_dict() tolerate undefined paramsSteve Reinhardt
2012-02-14MEM: Fix residual bus ports and make them master/slaveAndreas Hansson
2012-02-13BPred: Fix RAS to handle predicated call/return instructions.Mrinmoy Ghosh
2012-02-13BP: Fix several Branch Predictor issues.Mrinmoy Ghosh
2012-02-13MEM: Explicit ports and Python binding on CopyEngineAndreas Hansson
2012-02-13MEM: Pass the ports from Python to C++ using the Swig paramsAndreas Hansson
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
2012-02-12X86: open flags: Another patch from Vince WeaverGabe Black
2012-02-12cpu: add separate stats for insts/ops both globally and per cpu modelAnthony Gutierrez
2012-02-12mem: fix cache stats to use request ids correctlyDam Sunwoo
2012-02-12mem: Add a master ID to each request object.Ali Saidi
2012-02-12prefetcher: Make prefetcher a sim object instead of it being a parameter on c...Mrinmoy Ghosh
2012-02-11SPARC: Make PSTATE and HPSTATE a BitUnion.Gabe Black
2012-02-10Ruby: Remove isTagPresent() calls from Sequencer.ccNilay Vaish
2012-02-10MESI: Add queues for stalled requestsNilay Vaish
2012-02-10sim/system: initialize the pagePtr variableNilay Vaish
2012-02-10O3 CPU: Improve handling of delayed commit flagNilay Vaish
2012-02-10O3 CPU: Strengthen condition for handling interruptsNilay Vaish
2012-02-10O3 CPU: Provide the squashing instructionNilay Vaish
2012-02-10O3 Fetch: Check if PC is pointing to Microcode ROMNilay Vaish
2012-02-10SE/FS: Record the system pointer all the time for the simple CPU.Gabe Black
2012-02-09MEM: Remove onRetryList from BusPort and rely on retryListAndreas Hansson
2012-02-07Checker: Access workload element 0 only if there is an element 0.Gabe Black
2012-02-07Faults: Turn off arch/faults.hhGabe Black
2012-02-03System: Forgot to qrefresh with my last change.Gabe Black
2012-02-02System: Fix the check which detects running out of physical memory.Gabe Black
2012-02-01configs: More fixes for the memory system updatesAli Saidi
2012-01-31Merge with head, hopefully the last time for this batch.Gabe Black
2012-01-31clang: Enable compiling gem5 using clang 2.9 and 3.0Koan-Sin Tan