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AgeCommit message (Expand)Author
2018-11-14mem-cache: Move access latency calculation to CacheDaniel R. Carvalho
2018-11-14arch-arm: Print register name when warning on AT instructionsGiacomo Travaglini
2018-11-14mem-cache: implement a probe-based interfaceJavier Bueno
2018-11-14sim: Move BitUnion overloading to show/parseParamsGiacomo Travaglini
2018-11-14sim: Move paramIn/Out definition to header fileGiacomo Travaglini
2018-11-13cpu: Fixed PC shifting on LTAGE branch predictorPau Cabre
2018-11-13mem-cache: Align how we handle requests in atomic with timingNikos Nikoleris
2018-11-12systemc: Push python headers on top of sourcesGiacomo Travaglini
2018-11-12systemc: Stop using python to set/manage the global time resolution.Gabe Black
2018-11-12sim: Push the global frequency management code into C++.Gabe Black
2018-11-09systemc: Get rid of a duplicated base class initializer for sc_fifo.Gabe Black
2018-11-09systemc: Add a missing "const" on one of the sc_event operators.Gabe Black
2018-11-09systemc: Only build python utility code if python is enabled.Gabe Black
2018-11-09systemc: Separate and conditionalize exposing sc_main to python.Gabe Black
2018-11-09systemc: Seperate out the sc_main fiber and its bookkeeping.Gabe Black
2018-11-09systemc: Stop using python init to set up predefined message ids.Gabe Black
2018-11-09systemc: Wrap some report maps in functions.Gabe Black
2018-11-07mem-ruby: Use Packet writing functions instead of memcpyDaniel R. Carvalho
2018-11-07arch-arm: Deprecate usage of legacy bootloader patchingGiacomo Travaglini
2018-11-07arch-arm: ArmSystem::resetAddr64 renamed to be used in AArch32Giacomo Travaglini
2018-11-07arch-arm: Implement AArch32 RVBARGiacomo Travaglini
2018-11-07arch-arm: Remove SCTLR.VE bitGiacomo Travaglini
2018-11-07arch-arm: Refactor ISA::clear by adding a ISA::clear32 methodGiacomo Travaglini
2018-11-07arch-arm: Remove MISCREG commented numbersGiacomo Travaglini
2018-11-06mips: Change the integer and fp register widths to be 64 bits.Gabe Black
2018-11-06mips: Clean up type overrides for operands.Gabe Black
2018-11-06mips: Explicitly truncate the syscall return value down to 32 bits.Gabe Black
2018-11-05null: Claim to use 64 bit floating point registers.Gabe Black
2018-11-05sparc: Switch the FloatReg and FloatRegBits types to be 64 bit.Gabe Black
2018-11-05base: Add standard types for floating and nonfloating point register values.Gabe Black
2018-11-05systemc: Enable systemc support by default.Gabe Black
2018-11-05systemc: Explicitly keep the sc_port bind alongside sc_in's version.Gabe Black
2018-11-05systemc: Change how SC_BIND_PROXY_NIL is initialized.Gabe Black
2018-11-05systemc: Get rid of implementations for some disabled sc_vector methods.Gabe Black
2018-11-05systemc: Move a function after the class it uses internally.Gabe Black
2018-11-05systemc: Get rid of an unused private member in sc_clock.Gabe Black
2018-11-05mem-cache: Rename the tag class init function to tagsInit.Gabe Black
2018-11-05mem: Use Packet writing functions instead of memcpyDaniel R. Carvalho
2018-11-05mem-cache: Fix double block invalidationDaniel R. Carvalho
2018-11-05arch, arm: Return s1Req upon fault in s2LookupAnouk Van Laer
2018-11-05arch, arm: Effect of AT instructions on descriptor handlingAnouk Van Laer
2018-10-30syscall_emul: fix openat when directory does not end in "/"Ciro Santilli
2018-10-29syscall_emul: implement arm openatCiro Santilli
2018-10-29arch-arm: FIXUP for the add PRFM PST instruction commitYuetsu Kodama
2018-10-26mem-ruby: Fix MOESI_CMP_directory in ports orderNikos Nikoleris
2018-10-26arch-arm: We add PRFM PST instruction for armyuetsu.kodama
2018-10-26arch-arm: IMPDEF for SYS instruction with CRn = {11, 15}Giacomo Travaglini
2018-10-26arch-arm: AArch64 Instruction for MISCREG_IMPDEF_UNIMPLGiacomo Travaglini
2018-10-26arch-arm: Refactor AArch64 MSR/MRS trappingGiacomo Travaglini
2018-10-26arch-arm: Trap to EL2 only if not in Secure StateGiacomo Travaglini