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AgeCommit message (Expand)Author
2016-02-10mem: Be less conservative in clearing load locks in the cacheAndreas Hansson
2016-02-10mem: Move the point of coherency to the coherent crossbarAndreas Hansson
2016-02-10mem: Align cache behaviour in atomic when upstream is respondingAndreas Hansson
2016-02-10mem: Align how snoops are handled when hitting writebacksAndreas Hansson
2016-02-10mem: Deduce if cache should forward snoopsAndreas Hansson
2016-02-08scons: always generate sim/tags.ccCurtis Dunham
2016-02-06x86: revamp cmpxchg8b/cmpxchg16b implementationAlexandru Dutu
2016-02-06arch, x86: add support for arrays as memory operandsSteve Reinhardt
2016-02-06arch: get rid of dummy var initSteve Reinhardt
2016-02-06syscall_emul: fix bug in aux vector initializationSteve Reinhardt
2016-02-06style: eliminate explicit boolean comparisonsSteve Reinhardt
2016-02-06x86: create function to check miscreg validitySteve Reinhardt
2016-02-06style: fix missing spaces in control statementsSteve Reinhardt
2016-02-06style: remove trailing whitespaceSteve Reinhardt
2016-02-06dist, dev: add an ethernet switch modelMohammad Alian
2016-01-22ruby: removed Write_Only AccessPermissionBrad Beckmann
2015-07-20ruby: split CPU and GPU latency statsDavid Hashe
2016-01-19gpu-compute: AMD's baseline GPU modelTony Gutierrez
2016-01-19mem: write combining for ruby protocolsTony Gutierrez
2016-01-19* * *Tony Gutierrez
2015-07-20mem: misc flags for AMD gpu modelBlake Hechtman
2016-01-17sim: fix redundant --debug-start help stringSteve Reinhardt
2016-01-17cpu. arch: add initiateMemRead() to ExecContext interfaceSteve Reinhardt
2016-01-17cpu: remove unnecessary data ptr from O3 internal read() funcsSteve Reinhardt
2016-01-17arch: don't call *Timing functions from *Atomic versionsSteve Reinhardt
2016-01-17arch: get rid of unused LargestRead typedefSteve Reinhardt
2016-01-17sim: don't ignore SIG_TRAPSteve Reinhardt
2016-01-15dev, arm: Add a platform with support for both aarch32 and aarch64Andreas Sandberg
2016-01-15dev, arm: Add support for automatic PCI interrupt routingAndreas Sandberg
2016-01-11mem: fix bug in packet access endianness changesSteve Reinhardt
2016-01-11scons: Enable -Wextra by defaultAndreas Hansson
2016-01-11ext: Replace gzstream with iostream3 from zlib to avoid LGPLAndreas Hansson
2016-01-07dev: Distributed Ethernet link for distributed gem5 simulationsGabor Dozsa
2016-01-07pseudo inst,util: Add optional key to initparam pseudo instructionGabor Dozsa
2015-12-31mem: add CacheVerbose debug flag, filter noisy DPRINTFsSteve Reinhardt
2015-12-31mem: Do not rely on the NeedsWritable flag for responsesAndreas Hansson
2015-12-31mem: Do not allocate space for packet data if not neededAndreas Hansson
2015-12-31mem: Do not alter cache block state on uncacheable snoopsAndreas Hansson
2015-12-31mem: Make cache terminology easier to understandAndreas Hansson
2015-07-20ruby: slicc: have a static MachineTypeTony Gutierrez
2015-07-20ruby: slicc: remove support for single machine, multiple typesTony Gutierrez
2015-12-28mem: Explicitly check MSHR snoops for cases not dealt withAndreas Hansson
2015-12-28mem: Remove unused cache squash functionalityAndreas Hansson
2015-12-28mem: Avoid unecessary checks when creating HardPFReq in cacheAndreas Hansson
2015-12-28mem: Do not use sender state to track forwarded snoops in cacheAndreas Hansson
2015-12-28mem: Fix cache sender state handling and add clarificationAndreas Hansson
2015-12-18arm: remote GDB: rationalize structure of register offsetsBoris Shingarov
2015-12-18sim: Use the old work item behavior by defaultAndreas Sandberg
2015-12-17mem: Fix memory allocation bug in deferred snoop handlingAndreas Hansson
2015-12-14sim: Add an option to forward work items to PythonAndreas Sandberg
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