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2016-02-10mem: Be less conservative in clearing load locks in the cacheAndreas Hansson
Avoid being overly conservative in clearing load locks in the cache, and allow writes to the line if they are from the same context. This is in line with ALPHA and ARM.
2016-02-10mem: Move the point of coherency to the coherent crossbarAndreas Hansson
This patch introduces the ability of making the coherent crossbar the point of coherency. If so, the crossbar does not forward packets where a cache with ownership has already committed to responding, and also does not forward any coherency-related packets that are not intended for a downstream memory controller. Thus, invalidations and upgrades are turned around in the crossbar, and the memory controller only sees normal reads and writes. In addition this patch moves the express snoop promotion of a packet to the crossbar, thus allowing the downstream cache to check the express snoop flag (as it should) for bypassing any blocking, rather than relying on whether a cache is responding or not.
2016-02-10mem: Align cache behaviour in atomic when upstream is respondingAndreas Hansson
Adopt the same flow as in timing mode, where the caches on the path to memory get to keep the line (if present), and we use the responderHadWritable flag to determine if we need to forward the (invalidating) packet or not.
2016-02-10mem: Align how snoops are handled when hitting writebacksAndreas Hansson
This patch unifies the snoop handling in case of hitting writebacks with how we handle snoops hitting in the tags. As a result, we end up using the same optimisation as the normal snoops, where we inform the downstream cache if we encounter a line in Modified (writable and dirty) state, which enables us to avoid sending out express snoops to invalidate any Shared copies of the line. A few regressions consequently change, as some transactions are sunk higher up in the cache hierarchy.
2016-02-10mem: Deduce if cache should forward snoopsAndreas Hansson
This patch changes how the cache determines if snoops should be forwarded from the memory side to the CPU side. Instead of having a parameter, the cache now looks at the port connected on the CPU side, and if it is a snooping port, then snoops are forwarded. Less error prone, and less parameters to worry about. The patch also tidies up the CPU classes to ensure that their I-side port is not snooping by removing overrides to the snoop request handler, such that snoop requests will panic via the default MasterPort implement
2016-02-08scons: always generate sim/tags.ccCurtis Dunham
Due to insufficient build deps, the checkpoint tags might not get updated; this commit solves this. Due to the uncommon nature of the build target, regenerating tags.cc is a fairly clean solution. Since SCons hashes file contents, it won't recompile anything unless a new checkpoint upgrader is actually added. --HG-- extra : amend_source : ed3879da7668554693f697076deaf5029cc9b954
2016-02-06x86: revamp cmpxchg8b/cmpxchg16b implementationAlexandru Dutu
The previous implementation did a pair of nested RMW operations, which isn't compatible with the way that locked RMW operations are implemented in the cache models. It was convenient though in that it didn't require any new micro-ops, and supported cmpxchg16b using 64-bit memory ops. It also worked in AtomicSimpleCPU where atomicity was guaranteed by the core and not by the memory system. It did not work with timing CPU models though. This new implementation defines new 'split' load and store micro-ops which allow a single memory operation to use a pair of registers as the source or destination, then uses a single ldsplit/stsplit RMW pair to implement cmpxchg. This patch requires support for 128-bit memory accesses in the ISA (added via a separate patch) to support cmpxchg16b.
2016-02-06arch, x86: add support for arrays as memory operandsSteve Reinhardt
Although the cache models support wider accesses, the ISA descriptions assume that (for the most part) memory operands are integer types, which makes it difficult to define instructions that do memory accesses larger than 64 bits. This patch adds some generic support for memory operands that are arrays of uint64_t, and specifically a 'u2qw' operand type for x86 that is an array of 2 uint64_ts (128 bits). This support is unused at this point, but will be needed shortly for cmpxchg16b. Ideally the 128-bit SSE memory accesses will also be rewritten to use this support. Support for 128-bit accesses could also have been added using the gcc __int128_t extension, which would have been less disruptive. However, although clang also supports __int128_t, it's still non-standard. Also, more importantly, this approach creates a path to defining 256- and 512-byte operands as well, which will be useful for eventual AVX support.
2016-02-06arch: get rid of dummy var initSteve Reinhardt
MemOperand variables were being initialized to 0 "to avoid 'uninitialized variable' errors" but these no longer seem to be a problem (with the exception of one use case in POWER that is arguably broken and easily fixed here). Getting rid of the initialization is necessary to set up a subsequent patch which extends memory operands to possibly not be scalars, making the '= 0' initialization no longer feasible.
2016-02-06syscall_emul: fix bug in aux vector initializationSteve Reinhardt
Writing 16 bytes from an 8-byte source value is a bad idea. This doesn't appear to have broken anything, but showed up as spurious differences when tracediffing runs.
2016-02-06style: eliminate explicit boolean comparisonsSteve Reinhardt
Result of running 'hg m5style --skip-all --fix-control -a' to get rid of '== true' comparisons, plus trivial manual edits to get rid of '== false'/'== False' comparisons. Left a couple of explicit comparisons in where they didn't seem unreasonable: invalid boolean comparison in src/arch/mips/interrupts.cc:155 >> DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc) == true\n");<< invalid boolean comparison in src/unittest/unittest.hh:110 >> "EXPECT_FALSE(" #expr ")", (expr) == false)<<
2016-02-06x86: create function to check miscreg validitySteve Reinhardt
In the process of trying to get rid of an '== false' comparison, it became apparent that a slightly more involved solution was needed. Split this out into its own changeset since it's not a totally trivial local change like the others.
2016-02-06style: fix missing spaces in control statementsSteve Reinhardt
Result of running 'hg m5style --skip-all --fix-control -a'.
2016-02-06style: remove trailing whitespaceSteve Reinhardt
Result of running 'hg m5style --skip-all --fix-white -a'.
2016-02-06dist, dev: add an ethernet switch modelMohammad Alian
2016-01-22ruby: removed Write_Only AccessPermissionBrad Beckmann
2015-07-20ruby: split CPU and GPU latency statsDavid Hashe
2016-01-19gpu-compute: AMD's baseline GPU modelTony Gutierrez
2016-01-19mem: write combining for ruby protocolsTony Gutierrez
This patch adds support for write-combining in ruby.
2016-01-19* * *Tony Gutierrez
mem: support for gpu-style RMWs in ruby This patch adds support for GPU-style read-modify-write (RMW) operations in ruby. Such atomic operations are traditionally executed at the memory controller (instead of through an L1 cache using cache-line locking). Currently, this patch works by propogating operation functors through the memory system.
2015-07-20mem: misc flags for AMD gpu modelBlake Hechtman
This patch add support to mark memory requests/packets with attributes defined in HSA, such as memory order and scope.
2016-01-17sim: fix redundant --debug-start help stringSteve Reinhardt
Just changes the metavar for --debug-start from TIME to TICK in cset 72046b9b3323 and didn't notice that the comment "must be in ticks" is now redundant.
2016-01-17cpu. arch: add initiateMemRead() to ExecContext interfaceSteve Reinhardt
For historical reasons, the ExecContext interface had a single function, readMem(), that did two different things depending on whether the ExecContext supported atomic memory mode (i.e., AtomicSimpleCPU) or timing memory mode (all the other models). In the former case, it actually performed a memory read; in the latter case, it merely initiated a read access, and the read completion did not happen until later when a response packet arrived from the memory system. This led to some confusing things, including timing accesses being required to provide a pointer for the return data even though that pointer was only used in atomic mode. This patch splits this interface, adding a new initiateMemRead() function to the ExecContext interface to replace the timing-mode use of readMem(). For consistency and clarity, the readMemTiming() helper function in the ISA definitions is renamed to initiateMemRead() as well. For x86, where the access size is passed in explicitly, we can also get rid of the data parameter at this level. For other ISAs, where the access size is determined from the type of the data parameter, we have to keep the parameter for that purpose.
2016-01-17cpu: remove unnecessary data ptr from O3 internal read() funcsSteve Reinhardt
The read() function merely initiates a memory read operation; the data doesn't arrive until the access completes and a response packet is received from the memory system. Thus there's no need to provide a data pointer; its existence is historical. Getting this pointer out of this internal o3 interface sets the stage for similar cleanup in the ExecContext interface. Also found that we were pointlessly setting the contents at this pointer on a store forward (the useful memcpy happens just a few lines below the deleted one).
2016-01-17arch: don't call *Timing functions from *Atomic versionsSteve Reinhardt
The readMemAtomic/writeMemAtomic helper functions were calling readMemTiming/writeMemTiming respectively. This is functionally correct, since the *Timing functions are doing the same access initiation operation as the *Atomic functions (just that the *Atomic versions also complete the access in line). It also provides for some (very minimal) code reuse. Unfortunately, it's potentially pretty confusing, since it makes it look like the atomic accesses are somehow being converted to timing accesses. It also gets in the way of specializing the timing interface (as will be done in a future patch).
2016-01-17arch: get rid of unused LargestRead typedefSteve Reinhardt
2016-01-17sim: don't ignore SIG_TRAPSteve Reinhardt
By ignoring SIG_TRAP, using --debug-break <N> when not connected to a debugger becomes a no-op. Apparently this was intended to be a feature, though the rationale is not clear. If we don't ignore SIG_TRAP, then using --debug-break <N> when not connected to a debugger causes the simulation process to terminate at tick N. This is occasionally useful, e.g., if you just want to collect a trace for a specific window of execution then you can combine this with --debug-start to do exactly that. In addition to not ignoring the signal, this patch also updates the --debug-break help message and deletes a handful of unprotected calls to Debug::breakpoint() that relied on the prior behavior.
2016-01-15dev, arm: Add a platform with support for both aarch32 and aarch64Andreas Sandberg
Add a platform with support for both aarch32 and aarch64. This platform implements a subset of the devices in a real Versatile Express and extends it with some gem5-specific functionality. It is in many ways similar to the old VExpress_EMM64 platform, but supports the following new features: * Automatic PCI interrupt assignment * PCI interrupts allocated in a contiguous range. * Automatic boot loader selection (32-bit / 64-bit) * Cleaner memory map where gem5-specific devices live in CS5 which isn't used by current Versatile Express platforms. * No fake devices. Devices that were previously faked will be removed from the device tree instead. * Support for 510 GiB contiguous memory
2016-01-15dev, arm: Add support for automatic PCI interrupt routingAndreas Sandberg
Add support for automatic PCI interrupt routing using a device's ID on the PCI bus. Our current DTBs typically tell the kernel that we do this or something similar when declaring the PCI controller. This changeset adds an option to make the simulator behave in the same way. Interrupt routing can be selected by setting the int_policy parameter in the GenericArmPciHost. The following values are supported: * ARM_PCI_INT_STATIC: Use the old static routing policy using the interrupt line from a device's configurtion space. * ARM_PCI_INT_DEV: Use device number on the PCI bus to map to an interrupt in the GIC. The interrupt is computed as: gic_int = int_base + (pci_dev % int_count) * ARM_PCI_INT_PIN: Use device interrupt pin on the PCI bus to map to an interrupt in the GIC. The PCI specification reserves pin ID 0 for devices without interrupts, the interrupt therefore computed as: gic_int = int_base + ((pin - 1) % int_count)
2016-01-11mem: fix bug in packet access endianness changesSteve Reinhardt
The new Packet::setRaw() method incorrectly still contained an htog() conversion. As a result, calls to the old set() method (now defined as setRaw(htog(v))) underwent two htog conversions, which breaks things when htog() is not a no-op. Interestingly the only test that caught this was a SPARC boot test, where an IsaFake device with a non-zero return value was getting swapped twice resulting in a register getting loaded with 0x100000000000000 instead of 1. (Good reason for keeping SPARC around, perhaps?)
2016-01-11scons: Enable -Wextra by defaultAndreas Hansson
Make best use of the compiler, and enable -Wextra as well as -Wall. There are a few issues that had to be resolved, but they are all trivial.
2016-01-11ext: Replace gzstream with iostream3 from zlib to avoid LGPLAndreas Hansson
This patch replaces the gzstream zlib wrapper with the iostream3 wrapper provided as part of zlib contributions. The main reason for the switch is to avoid including LGPL in the default gem5 build. iostream3 is provided under a more permissive license: The code is provided "as is", with the permission to use, copy, modify, distribute and sell it for any purpose without fee.
2016-01-07dev: Distributed Ethernet link for distributed gem5 simulationsGabor Dozsa
Distributed gem5 (abbreviated dist-gem5) is the result of the convergence effort between multi-gem5 and pd-gem5 (from Univ. of Wisconsin). It relies on the base multi-gem5 infrastructure for packet forwarding, synchronisation and checkpointing but combines those with the elaborated network switch model from pd-gem5. --HG-- rename : src/dev/net/multi_etherlink.cc => src/dev/net/dist_etherlink.cc rename : src/dev/net/multi_etherlink.hh => src/dev/net/dist_etherlink.hh rename : src/dev/net/multi_iface.cc => src/dev/net/dist_iface.cc rename : src/dev/net/multi_iface.hh => src/dev/net/dist_iface.hh rename : src/dev/net/multi_packet.hh => src/dev/net/dist_packet.hh
2016-01-07pseudo inst,util: Add optional key to initparam pseudo instructionGabor Dozsa
The key parameter can be used to read out various config parameters from within the simulated software.
2015-12-31mem: add CacheVerbose debug flag, filter noisy DPRINTFsSteve Reinhardt
Some of the DPRINTFs added to the classic cache in cset 45df88079f04, while useful to those unfamiliar with the cache code, end up being noise when you're familiar with the code but are trying to debug tricky protocol issues. (Particularly getting two messages from each cache as it receives a snoop request then declares that there was no match.) This patch introduces a CacheVerbose debug flag, and moves a subset of the added DPRINTFs into that category, so that Cache by itself returns to being a more succinct summary of cache activity. Also added a CacheAll compound flag to turn on all the cache-related debug flags (other than CacheTags, which you *really* have to want badly to turn it on, IMO).
2015-12-31mem: Do not rely on the NeedsWritable flag for responsesAndreas Hansson
This patch removes the NeedsWritable flag for all responses, as it is really only the request that needs a writable response. The response, on the other hand, should in these cases always provide the line in a writable state, as indicated by the hasSharers flag not being set. When we send requests that has NeedsWritable set, the response will always have the hasSharers flag not set. Additionally, there are cases where the request did not have NeedsWritable set, and we still get a writable response with the hasSharers flag not set. This never happens on snoops, but is used by downstream caches to pass ownership upstream. As part of this patch, the affected response types are updated, and the snoop filter is similarly modified to check only the hasSharers flag (as it should). A sanity check is also added to the packet class, asserting that we never look at the NeedsWritable flag for responses. No regressions are affected.
2015-12-31mem: Do not allocate space for packet data if not neededAndreas Hansson
This patch looks at the request and response command to determine if either actually has any data payload, and if not, we do not allocate any space for packet data. The only tricky case is where the command type is changed as part of the MSHR functionality. In these cases where the original packet had no data, but the new packet does, we need to explicitly call allocate().
2015-12-31mem: Do not alter cache block state on uncacheable snoopsAndreas Hansson
This patch ensures we do not respond with a Modified (dirty and writable) line if the request is uncacheable, and that the cache responding retains the line without modifying the state (even if responding).
2015-12-31mem: Make cache terminology easier to understandAndreas Hansson
This patch changes the name of a bunch of packet flags and MSHR member functions and variables to make the coherency protocol easier to understand. In addition the patch adds and updates lots of descriptions, explicitly spelling out assumptions. The following name changes are made: * the packet memInhibit flag is renamed to cacheResponding * the packet sharedAsserted flag is renamed to hasSharers * the packet NeedsExclusive attribute is renamed to NeedsWritable * the packet isSupplyExclusive is renamed responderHadWritable * the MSHR pendingDirty is renamed to pendingModified The cache states, Modified, Owned, Exclusive, Shared are also called out in the cache and MSHR code to make it easier to understand.
2015-07-20ruby: slicc: have a static MachineTypeTony Gutierrez
This patch is imported from reviewboard patch 2551 by Nilay. This patch moves from a dynamically defined MachineType to a statically defined one. The need for this patch was felt since a dynamically defined type prevents us from having types for which no machine definition may exist. The following changes have been made: i. each machine definition now uses a type from the MachineType enumeration instead of any random identifier. This required changing the grammar and the *.sm files. ii. MachineType enumeration defined statically in RubySlicc_Exports.sm. * * * normal protocol fixes for nilay's parser machine type fix
2015-07-20ruby: slicc: remove support for single machine, multiple typesTony Gutierrez
This patch is imported from reviewboard patch 2550 by Nilay. It was possible to specify multiple machine types with a single state machine. This seems unnecessary and is being removed.
2015-12-28mem: Explicitly check MSHR snoops for cases not dealt withAndreas Hansson
Add a sanity check to make it explicit that we currently do not allow an I/O coherent agent to directly issue writes into the coherent part of the memory system (it has to go via a cache, and get transformed into a read ex, upgrade or invalidation).
2015-12-28mem: Remove unused cache squash functionalityAndreas Hansson
This patch removes the unused squash function from the MSHR queue, and the associated (and also unused) threadNum member from the MSHR.
2015-12-28mem: Avoid unecessary checks when creating HardPFReq in cacheAndreas Hansson
The checks made before sending out a HardPFReq were unecessarily complex, and checked for cases that never occur. This patch tidies it up.
2015-12-28mem: Do not use sender state to track forwarded snoops in cacheAndreas Hansson
This patch changes how the cache tracks which snoops are forwarded, and which ones are created locally. Previously the identification was based on an empty sender state of a specific class, but this method fails to distinguish which cache actually attached the sender state. Instead we use the same mechanism as the crossbar, and keep track of the requests that have outstanding snoops.
2015-12-28mem: Fix cache sender state handling and add clarificationAndreas Hansson
This patch addresses a bug in how the cache attached the MSHR as a sender state. Rather than overwriting any existing sender state it now pushes a new one. The handling of upward snoops is also clarified.
2015-12-18arm: remote GDB: rationalize structure of register offsetsBoris Shingarov
Currently, the wire format of register values in g- and G-packets is modelled using a union of uint8/16/32/64 arrays. The offset positions of each register are expressed as a "register count" scaled according to the width of the register in question. This results in counter- intuitive and error-prone "register count arithmetic", and some formats would even be altogether unrepresentable in such model, e.g. a 64-bit register following a 32-bit one would have a fractional index in the regs64 array. Another difficulty is that the array is allocated before the actual architecture of the workload is known (and therefore before the correct size for the array can be calculated). With this patch I propose a simpler mechanism for expressing the register set structure. In the new code, GdbRegCache is an abstract class; its subclasses contain straightforward structs reflecting the register representation. The determination whether to use e.g. the AArch32 vs. AArch64 register set (or SPARCv8 vs SPARCv9, etc.) is made by polymorphically dispatching getregs() to the concrete subclass. The subclass is not instantiated until it is needed for actual g-/G-packet processing, when the mode is already known. This patch is not meant to be merged in on its own, because it changes the contract between src/base/remote_gdb.* and src/arch/*/remote_gdb.*, so as it stands right now, it would break the other architectures. In this patch only the base and the ARM code are provided for review; once we agree on the structure, I will provide src/arch/*/remote_gdb.* for the other architectures; those patches could then be merged in together. Review Request: http://reviews.gem5.org/r/3207/ Pushed by Joel Hestness <jthestness@gmail.com>
2015-12-18sim: Use the old work item behavior by defaultAndreas Sandberg
When adding an option to forward work items to the Python environment, the new behavior was accidentally enabled by default. Set the value of exit_on_work_items to False by default to revert to the old behavior unless the simulation scripts explicitly requests work item forwarding.
2015-12-17mem: Fix memory allocation bug in deferred snoop handlingAndreas Hansson
This patch fixes a corner case in the deferred snoop handling, where requests ended up being used by multiple packets with different lifetimes, and inadvertently got deleted while they were still in use.
2015-12-14sim: Add an option to forward work items to PythonAndreas Sandberg
There are cases where we want the Python world to handle work items instead of the C++ world. However, that's currently not possible. This changeset adds the forward_work_items option to the System class. Then it is set to True, work items will generate workbegin/workend simulation exists with the work item ID as the exit code and the old C++ handling is completely bypassed. --HG-- extra : rebase_source : 8de637a744fc4b6ff2bc763f00cdf8ddf2bff885