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2012-08-28Checker: Fix checker CPU portsAndreas Hansson
This patch updates how the checker CPU handles the ports such that the regressions will once again run without causing a panic. A minor amount of tidying up was also done as part of this patch.
2012-08-28swig: Disable unused value warning with llvm 3.1 compilersAndreas Hansson
This patch disables a warning for unused values which causes problems when compiling the swig-generated sources using recent llvm-based compilers like llvm-gcc and clang.
2012-08-27sim: fix overflow check in simulate because Tick is now unsignedAnthony Gutierrez
2012-08-27Ruby: remove README.debugging and Decommissioning_noteNilay Vaish
These files were relevant when Ruby was part of GEMS. They are not required any longer.
2012-08-27System: Remove redundant call to startupCPUNilay Vaish
2012-08-27Ruby: Remove RubyEventQueueNilay Vaish
This patch removes RubyEventQueue. Consumer objects now rely on RubySystem or themselves for scheduling events.
2012-08-27Ruby Memory Vector: Allow more than 4GB of memoryNilay Vaish
The memory size variable was a 32-bit int. This meant that the size of the memory was limited to 4GB. This patch changes the type of the variable to 64-bit to support larger memory sizes. Thanks to Raghuraman Balasubramanian for bringing this to notice.
2012-08-25MESI Protocol: Correct the virtual network in profile functionsNilay Vaish
The virtual network in a couple of places was incorrectly mentioned as 3 in place of 1. This is being corrected.
2012-08-25MESI Coherence Protocol: Add copyright noticeNilay Vaish
2012-08-22DMA: Refactor the DMA device and align timing and atomicAndreas Hansson
This patch does a bunch of house-keeping updates on the DMA, including indentation, and formatting, but most importantly breaks out the response handling such that it can be shared between the atomic and timing modes. It also removes a potential bug caused by the atomic handling of responses only deleting the allocated request (pkt->req) once the DMA action completes instead of doing so for every packet. Before this patch, the handling of responses was near identical for atomic and timing, but the code was simply duplicated. With this patch, the handleResp method deals with the responses in both cases. There are further updates to make after removing the NACKs, but that will be part of a separate follow-up patch. This patch does not change the behaviour of any regression.
2012-08-22Packet: Remove NACKs from packet and its use in endpointsAndreas Hansson
This patch removes the NACK frrom the packet as there is no longer any module in the system that issues them (the bridge was the only one and the previous patch removes that). The handling of NACKs was mostly avoided throughout the code base, by using e.g. panic or assert false, but in a few locations the NACKs were actually dealt with (although NACKs never occured in any of the regressions). Most notably, the DMA port will now never receive a NACK and the backoff time is thus never changed. As a consequence, the entire backoff mechanism (similar to a PCI bus) is now removed and the DMA port entirely relies on the bus performing the arbitration and issuing a retry when appropriate. This is more in line with e.g. PCIe. Surprisingly, this patch has no impact on any of the regressions. As mentioned in the patch that removes the NACK from the bridge, a follow-up patch should change the request and response buffer size for at least one regression to also verify that the system behaves as expected when the bridge fills up.
2012-08-22Bridge: Remove NACKs in the bridge and unify with packet queueAndreas Hansson
This patch removes the NACKing in the bridge, as the split request/response busses now ensure that protocol deadlocks do not occur, i.e. the message-dependency chain is broken by always allowing responses to make progress without being stalled by requests. The NACKs had limited support in the system with most components ignoring their use (with a suitable call to panic), and as the NACKs are no longer needed to avoid protocol deadlocks, the cleanest way is to simply remove them. The bridge is the starting point as this is the only place where the NACKs are created. A follow-up patch will remove the code that deals with NACKs in the endpoints, e.g. the X86 table walker and DMA port. Ultimately the type of packet can be complete removed (until someone sees a need for modelling more complex protocols, which can now be done in parts of the system since the port and interface is split). As a consequence of the NACK removal, the bridge now has to send a retry to a master if the request or response queue was full on the first attempt. This change also makes the bridge ports very similar to QueuedPorts, and a later patch will change the bridge to use these. A first step in this direction is taken by aligning the name of the member functions, as done by this patch. A bit of tidying up has also been done as part of the simplifications. Surprisingly, this patch has no impact on any of the regressions. Hence, there was never any NACKs issued. In a follow-up patch I would suggest changing the size of the bridge buffers set in FSConfig.py to also test the situation where the bridge fills up.
2012-08-22Port: Extend the QueuedPort interface and use where appropriateAndreas Hansson
This patch extends the queued port interfaces with methods for scheduling the transmission of a timing request/response. The methods are named similar to the corresponding sendTiming(Snoop)Req/Resp, replacing the "send" with "sched". As the queues are currently unbounded, the methods always succeed and hence do not return a value. This functionality was previously provided in the subclasses by calling PacketQueue::schedSendTiming with the appropriate parameters. With this change, there is no need to introduce these extra methods in the subclasses, and the use of the queued interface is more uniform and explicit.
2012-08-21Device: Remove overloaded pio_latency parameterAndreas Hansson
This patch removes the overloading of the parameter, which seems both redundant, and possibly incorrect. The PciConfigAll now also uses a Param.Latency rather than a Param.Tick. For backwards compatibility it still sets the pio_latency to 1 tick. All the comments have also been updated to not state that it is in simticks when it is not necessarily the case.
2012-08-21CPU: Remove overloaded function_trace_start parameterAndreas Hansson
This patch removes the overloading of the parameter, which seems both redundant, and possibly incorrect. The inorder CPU is particularly interesting as it uses a different name for the parameter, and never make any use of it internally.
2012-08-21PacketQueue: Allow queuing in the same tick as desired send tickAndreas Hansson
This patch allows packets to be enqueued in the same tick as they are intended to be sent. This does not imply they actually are sent that tick, although that is possible. This change is useful for module that use the queued ports primarly to avoid handling the flow control involved in sending and retrying packets.
2012-08-21EventManager: Remove test for NULL pointer in constructorAndreas Hansson
This patch tidies up the EventManager constructor and prunes a corner case where the EventManager would initialise its eventq pointer to NULL. This would cause segmentation faults on actual use and should never happen.
2012-08-21Clock: Make Tick unsigned and remove UTickAndreas Hansson
This patch makes the Tick unsigned and removes the UTick typedef. The ticks should never be negative, and there was only one major issue with removing it, caused by the o3 CPU using a -1 as an initial value. The patch has no impact on any regressions.
2012-08-21Clock: Move the clock and related functions to ClockedObjectAndreas Hansson
This patch moves the clock of the CPU, bus, and numerous devices to the new class ClockedObject, that sits in between the SimObject and MemObject in the class hierarchy. Although there are currently a fair amount of MemObjects that do not make use of the clock, they potentially should do so, e.g. the caches should at some point have the same clock as the CPU, potentially with a 1:n ratio. This patch does not introduce any new clock objects or object hierarchies (clusters, clock domains etc), but is still a step in the direction of having a more structured approach clock domains. The most contentious part of this patch is the serialisation of clocks that some of the modules (but not all) did previously. This serialisation should not be needed as the clock is set through the parameters even when restoring from the checkpoint. In other words, the state is "stored" in the Python code that creates the modules. The nextCycle methods are also simplified and the clock phase parameter of the CPU is removed (this could be part of a clock object once they are introduced).
2012-08-19Ruby Banked Array: add copyrightsNilay Vaish
2012-08-16Ruby: Add RubySystem parameter to MemoryControlJason Power
This guarantees that RubySystem object is created before the MemoryController object is created.
2012-08-16Alpha System: override startup(), instead of loadState()Nilay Vaish
Alpha System was overriding loadState() function to setup some functional event. The system tried to read/write to memory before the Ruby memory had unserialized the state. With this patch, Alpha System overrides the startup() function, and sets up functional events in this function. This works because startup() is called after Ruby memory system has unserialized the memory state.
2012-08-15O3,ARM: fix some problems with drain/switchout functionality and add Drain ↵Anthony Gutierrez
DPRINTFs This patch fixes some problems with the drain/switchout functionality for the O3 cpu and for the ARM ISA and adds some useful debug print statements. This is an incremental fix as there are still a few bugs/mem leaks with the switchout code. Particularly when switching from an O3CPU to a TimingSimpleCPU. However, when switching from O3 to O3 cores with the ARM ISA I haven't encountered any more assertion failures; now the kernel will typically panic inside of simulation.
2012-08-15sysemul: bump all linux versions of for syscal emulation to 3.0.Ali Saidi
New tool chains seem to be looking for kernel versions newer than what this this was previously set to. Also take this opportunity to change the hostname we report in uname to sim.gem5.org.
2012-08-10Ruby: Clean up topology changesJason Power
This patch moves instantiateTopology into Ruby.py and removes the mem/ruby/network/topologies directory. It also adds some extra inheritance to the topologies to clean up some issues in the existing topologies.
2012-08-08System: set kernel to null, if unspecified.Nilay Vaish
2012-08-06syscall emulation: Enabled getrlimit and getrusage for x86.Marc Orr
Added/moved rlimit constants to base linux header file. This patch is a revised version of Vince Weaver's earlier patch.
2012-08-06SETranslatingPortProxy: fix bug in tryReadString()Steve Reinhardt
Off-by-one loop termination meant that we were stuffing the terminating '\0' into the std::string value, which makes for difficult-to-debug string comparison failures.
2012-08-06process: add progName() virtual functionSteve Reinhardt
This replaces a (potentially uninitialized) string field with a virtual function so that we can have a safe interface without requiring changes to the eio code.
2012-08-06syscall_emul: clean up open() code a bit.Steve Reinhardt
2012-08-06str: add an overloaded startswith() utility methodSteve Reinhardt
for various string types and use it in a few places.
2012-08-06syscall emulation: Clean up ioctl handling, and implement for x86.Marc Orr
Enable different whitelists for different OS/arch combinations, since some use the generic Linux definitions only, and others use definitions inherited from earlier Unix flavors on those architectures. Also update x86 function pointers so ioctl is no longer unimplemented on that platform. This patch is a revised version of Vince Weaver's earlier patch.
2012-08-01Ruby NetDest: add assert for bad element in netdestJason Power
2012-07-27dma: remove unused variableAnthony Gutierrez
this patch removes the actionInProgress field from the DmaPort class. this variable is only defined and initiated in the ctor. it is never used.
2012-07-27checker: make checker cpu id match its host's cpu idAnthony Gutierrez
when using the checker i ran into problems where an instruction reading the cpu id register failed because the ids did not match, and hence, the result of the instruction did not match. this patch ensures that the ids match so this instruction does not fail. this problem only seemed to manifest itself when multiple cores were in the system, either multi-core, or extra switched- out cores present in the system.
2012-07-27cache: don't allow dirty data in the i-cacheAnthony Gutierrez
removes the optimization that forwards an exclusive copy to a requester on a read, only for the i-cache. this optimization isn't necessary because we typically won't be writing to the i-cache.
2012-07-27ARM: fix value of MISCREG_CTR returned by readMiscReg()Anthony Gutierrez
According to the A15 TRM the value of this register is as follows (assuming 16 word = 64 byte lines) [31:29] Format - b100 specifies v7 [28] RAZ - b0 [27:24] CWG log2(max writeback size #words) - 0x4 16 words [23:20] ERG log2(max reservation size #words) - 0x4 16 words [19:16] DminLine log2(smallest dcache line #words) - 0x4 16 words [15:14] L1Ip L1 index/tagging policy - b11 specifies PIPT [13:4] RAZ - b0000000000 [3:0] IminLine log2(smallest icache line #words) - 0x4 16 words
2012-07-23Bridge: Use EventWrapper instead of Event subclass for sendEventAndreas Hansson
This class simply cleans up the code by making use of the EventWrapper convenience class to schedule the sendEvent in the bridge ports.
2012-07-22X86 CPUID: Return false if unknown processor familyNilay Vaish
2012-07-12Mem: Make SimpleMemory single portedAndreas Hansson
This patch changes the simple memory to have a single slave port rather than a vector port. The simple memory makes no attempts at modelling the contention between multiple ports, and any such multiplexing and demultiplexing could be done in a bus (or crossbar) outside the memory controller. This scenario also matches with the ongoing work on a SimpleDRAM model, which will be a single-ported single-channel controller that can be used in conjunction with a bus (or crossbar) to create a multi-port multi-channel controller. There are only very few regressions that make use of the vector port, and these are all for functional accesses only. To facilitate these cases, memtest and memtest-ruby have been updated to also have a "functional" bus to perform the (de)multiplexing of the functional memory accesses.
2012-07-12Ruby: remove config information from ruby.statsNilay Vaish
This patch removes printConfig() functions from all structures in Ruby. Most of the information is already part of config.ini, and where ever it is not, it would become in due course.
2012-07-12Ruby: remove some unused stuff from SLICC filesNilay Vaish
2012-07-11x86: added page size in bytes tlb entry functionBrad Beckmann
2012-07-11ruby: improved DRAM reset commentBrad Beckmann
2012-07-10syscall emulation: Add the futex system call.Marc Orr
2012-07-10x86: logSize and lruSeq are now optional ckpt paramsBrad Beckmann
2012-07-10Add hook to call map() on Process from python.Steve Reinhardt
This enables configuration scripts to set up mappings from process virtual addresses to specific physical addresses in SE mode. This feature is needed to support modeling of user-accessible memories or devices in SE mode, avoiding the complexities of FS mode and the need to write a device driver.
2012-07-10# User Brad Beckmann <Brad.Beckmann@amd.com>Brad Beckmann
ruby: fixed fatal print statement
2012-07-10ruby: remove the cpu assumptions for the random testerBrad Beckmann
2012-07-10# User Brad Beckmann <Brad.Beckmann@amd.com>Brad Beckmann
ruby: fixed msgptr print call