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AgeCommit message (Expand)Author
2014-01-24mem: per-thread cache occupancy and per-block agesDam Sunwoo
2014-01-24base: add support for probe points and common probesMatt Horsnell
2014-01-24sim: Expose the current voltage for each object as a statAndreas Hansson
2014-01-24sim: Expose the current clock period as a statAndreas Hansson
2014-01-24mem: track per-request latencies and access depths in the cache hierarchyMatt Horsnell
2014-01-24config: Make the Clock a Tick parameter like Latency/FrequencyAndreas Hansson
2014-01-24x86: Fix memory leak in table walkerAndreas Hansson
2014-01-24cpu: Relax check on squashed non-speculative instructionsAndreas Hansson
2014-01-24cpu: remove faulty simpoint basic block inst count assertionDam Sunwoo
2014-01-17ruby: remove unused label no_vectorNilay Vaish
2014-01-10ruby: move all statistics to stats.txt, eliminate ruby.statsNilay Vaish
2014-01-10stats: add function for adding two histogramsNilay Vaish
2014-01-09ruby: fix bug introduced to revision 8523754f8885Nilay Vaish
2014-01-08ruby: slicc: remove variable 'addr' used in calls to doTransitionNilay Vaish
2014-01-04ruby: add a three level MESI protocol.Nilay Vaish
2014-01-04ruby: rename MESI_CMP_directory to MESI_Two_LevelNilay Vaish
2014-01-04ruby: add support for clustersNilay Vaish
2014-01-04ruby: some small changesNilay Vaish
2014-01-03python: provide better error message for wrapped C++ methodsSteve Reinhardt
2014-01-03python: don't die on assignment to cloned objectSteve Reinhardt
2013-12-29sim: Add support for dynamic frequency scalingChristopher Torng
2013-12-29mips: Floating point convert bug fixChristopher Torng
2013-12-26ruby: fix bugs in mesi cmp directory protocolNilay Vaish
2013-12-20ruby: slicc: replace max_in_port_rank with number of inportsNilay Vaish
2013-12-20ruby: declare variables to be unsigned in Address.hhNilay Vaish
2013-12-20ruby: mesi: remove owner and sharer fields from directory tagsNilay Vaish
2013-12-03sim: reset stats after startupNilay Vaish
2013-12-03cpu: call BaseCPU startup() function in o3 cpuNilay Vaish
2013-11-29base: Fix race in PollQueue and remove SIGALRM workaroundAndreas Sandberg
2013-11-29base: Clean up signal handlingAndreas Sandberg
2013-11-26sim: correct ticksToCycles() function.Nilay Vaish
2013-10-15kvm: Set the perf exclude_host attribute if availableAndreas Sandberg
2013-11-26x86: Implementation of Int3 and Int_Ib in long modeChristian Menard
2013-11-26kvm: Remove the unused hostFreq member from BaseKvmCPUAndreas Sandberg
2013-11-25sim: simulate with multiple threads and event queuesSteve Reinhardt ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E%2C%20Ali%20Saidi%20%3CAli.Saidi%40ARM.com%3E)
2013-11-15cpu: allow the fetch buffer to be smaller than a cache lineAnthony Gutierrez
2013-11-15cpu: Fix Checker register index useAndreas Hansson
2013-11-14tests: suppress output on switcheroo testsSteve Reinhardt
2013-11-12sim: fix event priority name for debug-start optionAnthony Gutierrez
2013-11-01mem: Fixes for DRAM stats accountingAndreas Hansson
2013-11-01mem: Fix the LPDDR3 page sizeAndreas Hansson
2013-11-01mem: Adding stats for DRAM power calculationNeha Agarwal
2013-11-01mem: Unify request selection for read and write queuesNeha Agarwal
2013-11-01mem: Add a simple adaptive version of the open-page policyAndreas Hansson
2013-11-01mem: Just-in-time write scheduling in DRAM controllerNeha Agarwal
2013-11-01mem: Add tRRD as a timing parameter for the DRAM controllerAndreas Hansson
2013-11-01mem: Less conservative tRAS in DRAM configurationsAndreas Hansson
2013-11-01mem: Make tXAW enforcement less conservative and per rankAni Udipi
2013-11-01mem: Fix for 100% write threshold in DRAM controllerNeha Agarwal
2013-11-01mem: Pick the next DRAM request based on bank availabilityAndreas Hansson