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2018-12-03cpu: Change raw pointers to STL ContainersRekai Gonzalez-Alberquilla
This patch changes two members from being raw pointers to being STL containers. The reason behind, other than cleanlyness and arguable OO best practices is that containers have more intronspections capabilities than naked pointers do, as the size is known. Using STL containers adds little overhead and eases the automation of process during debugging (gdb). Change-Id: I4d9d3eedafa8b5e50ac512ea93b458a4200229f2 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13126 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-12-03arch-arm: correctly set floats from GDB on aarch64Ciro Santilli
aarch64 floating point registers are now stored as vector type, but this was not updated in the stub. Change-Id: I4a2bc1cea0eec9beeb5bbd49e2a868b9d5ed0a42 Reviewed-on: https://gem5-review.googlesource.com/c/14498 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-12-03base: increase the GDB buffer size dynamicallyCiro Santilli
The size was not large enough for the 'G' packet on aarch64, which the client sends to set registers. This would lead to the stub not to be able to find the end of the input packet and keep waiting forever. Change-Id: Icb149f15a6c769371ebcb6ec5fbebc6170c31fc6 Reviewed-on: https://gem5-review.googlesource.com/c/14497 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-12-03arch-arm: only change the pc address when GDB registers are setCiro Santilli
The entire pcState was being reset, which made the simulation incorrectly switch to aarch32 from aarch64. Change-Id: I9ba7dd0ed95bc6120d94393bba272e0cb8c081c5 Reviewed-on: https://gem5-review.googlesource.com/c/14496 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-12-03arch-arm: fix the aarch64 GDB stubCiro Santilli
The main change is to remove vector registers from the GDB stub. Those registers were intended for SVE, which is a new architecture feature and not yet treated by default on the GDB present in Ubuntu 18.04, and possibly not even on GDB master. As a result, aarch64 GDB stub connections would fail with: Remote 'g' packet reply is too long The correct way to support those registers is to send XML GDB target description files to the client. This feature is not yet available for any architecture, and should be implemented in future patches. Other smaller fixes are: * cpsr is uint32_t in aarch64 as well as arm * use M5_ATTR_PACKED on the register structs since they are being cast and sent as byte arrays Change-Id: I77cd8a98e322ecc60799e5b11fe5cd414d893cc7 Reviewed-on: https://gem5-review.googlesource.com/c/14495 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-11-30systemc: Disable systemc when using gcc versions older than 5.0.Gabe Black
These versions don't support the std::put_time function. Since versions of gcc older than 5.0 aren't going to be supported at all in the fairly near future, this should only be temporary. The number of people using both systemc and older versions of gcc should be very small, or even zero. Change-Id: Ie9572fdf83ba9569df6bc0457c98d86565dcdcd8 Reviewed-on: https://gem5-review.googlesource.com/c/14755 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-29base: Change the unit test binary names to use .test, and to be consistent.Gabe Black
Most tests were named *test where * was the base name of the file being tested, but some were named differently based on, for instance, the name of the class that file implemented. This change makes all the test names consistently based off of the file name they test, and also brings in the new .test convention to make them easier to read. Now, if you have a file like fiber.cc you want to test, you'd have a unit test in a file called fiber.test.cc, and a test called fiber.test which would generate a binary called fiber.test.opt, fiber.test.debug, etc. Change-Id: I61d59016090371a9bae72066e7473a34aecea21f Reviewed-on: https://gem5-review.googlesource.com/c/14677 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-29base: Rename unit test cc files to be *.test.cc.Gabe Black
This makes the name easier to read, looks ok if the file is named with underscores between words or not, is easy to grep for, and shouldn't introduce any ambiguities in the file names. Change-Id: I34b7bcccea2d87c10c0de417dd5e3ef27c4b5666 Reviewed-on: https://gem5-review.googlesource.com/c/14676 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-29base: Fix include order in the inifile unit test.Gabe Black
Even though gtest.h is a C++ header, it looks like a C header which makes the style check hook upset. Lets move it up so the hook doesn't complain when the file is changed. Change-Id: Ibcc2d0b7bf3b254c70e55b30379ebd4b70933c26 Reviewed-on: https://gem5-review.googlesource.com/c/14675 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-29systemc: Run the systemc tests directly from their build directories.Gabe Black
We were previously running them from the current directory to start with, and then having the config script switch to the build directory. That worked, except when output streams might be opened as part of the global constructors which would run before the config script. This change makes us start from the build directory directly, making the switch in the config script unnecessary and ensuring that no files leak outside of the build when running tests. Change-Id: I484168793bfc5abc4e5631fb3468733fb9d829af Reviewed-on: https://gem5-review.googlesource.com/c/14519 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-29systemc: Run the systemc tests with the CWD in the build directory.Gabe Black
This will prevent some (but not all) output files the tests generate from ending up outside the build directory. Because some output file streams are constructed as global objects, their paths are resolved relative to the CWD when gem5 starts, before the config script has a chance to change it. Subsequent changes will make verify.py should make gem5 start with the correct working directory, cleaning up the remaining leaking files. Change-Id: I75a1256719dab4c98ab868c209d09b9dcdabb458 Reviewed-on: https://gem5-review.googlesource.com/c/14518 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-29systemc: Add DEPS files for some tests with non-source file dependencies.Gabe Black
This ensures that those files will be available when running the test relative to its build directory. Change-Id: If775ca328b3e1165baa968e4b39c36db0172837c Reviewed-on: https://gem5-review.googlesource.com/c/14517 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-29systemc: Make verify.py recognize a DEPS file in test dirs.Gabe Black
This file lists additional files beyond the sources that the test relies on, like files it uses when running. Change-Id: Ifc4958b26eed08689e0e72bd87f84388dbcf1898 Reviewed-on: https://gem5-review.googlesource.com/c/14516 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-28base: Add missing overrides in statistics headerNikos Nikoleris
Change-Id: Id5ee2a970a3dceee1b7e24ce3b452b7fece87875 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14619 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-28arch-arm: Add missing template declarationNikos Nikoleris
The lack of a template declaration for IllegalInstSetStateFault was causing errors when compiling with clang. Change-Id: If7f19d7e879330226c80df2baca73d88d818f673 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14618 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-11-28cpu: Added new stats to TAGE and LTAGE branch predictorsPau Cabre
They are basically used to tell wich component of the predictor is providing the prediction and whether it is correct or wrong Change-Id: I7b3db66535f159091f1b37d70c2d942d50b20fb2 Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14535 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-28cpu: split LTAGE implementation into a base TAGE and a derived LTAGEPau Cabre
The new derived LTAGE is equivalent to the original LTAGE implementation The default values of the TAGE branch predictor match the settings of the 8C-TAGE configuration described in https://www.jilp.org/vol8/v8paper1.pdf Change-Id: I8323adbfd5c9a45db23cfff234218280e639f9ed Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14435 Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-28cpu,arch-arm: Initialise data membersRekai Gonzalez-Alberquilla
The value that is not initialized has a bogus value that manifests when using some debug-flags what makes the usage of tracediff a bit more challenging. In addition, while debugging with other techniques, it introduces the problem of understanding if the value of a field is 'intended' or just an effect of the lack of initialisation. Change-Id: Ied88caa77479c6f1d5166d80d1a1a057503cb106 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13125 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-11-28arch-arm: clang compilation fixesMatteo Andreozzi
Fix 1: std::pair constructor is not a constexpr in clang implementation Fix 2: static const templates need to be defined in their translation unit Change-Id: I3d9b9b47e1d148e44555f40e2e2aeff06707ff8f Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14617 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-11-28tests: Convert IniFile unit test to a GTestGiacomo Travaglini
Change-Id: I47d6c9cbae21877420a15ffcf8489e3c26959139 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14615 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-27hsail: Fix a warning/build failure for HSAIL_X86.Gabe Black
The Bitselect operation definition used ~ to invert the bits of a mask value, but if that mask value is of type bool, that generates a warning. This change casts that value to a uint64_t so that it can always have ~ applied to it. Change-Id: I7fbfc6ff264bc32a265f2724c772b8fae08590f7 Reviewed-on: https://gem5-review.googlesource.com/c/14655 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-27arch, base, cpu, gpu, mem: Replace assert(0 or false with panic.Gabe Black
Neither assert(0) nor assert(false) give any hint as to why control getting to them is bad, and their more descriptive versions, assert(0 && "description") and assert(false && "description"), jury rig assert to add an error message when the utility function panic() already does that directly with better formatting options. This change replaces that flavor of call to assert with panic, except in the actual code which processes the formatting that panic uses (to avoid infinitely recurring error handling), and in some *.sm files since I don't know what rules those have to follow and don't want to accidentaly break them. Change-Id: I8addfbfaf77eaed94ec8191f2ae4efb477cefdd0 Reviewed-on: https://gem5-review.googlesource.com/c/14636 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-27sim-se: only implement getdentsFunc on supported hostsCiro Santilli
The implementation of the getdents syscall relies on SYS_getdents, which is not available on all archs, because the getdents syscall has been superseded by getdents64, and does not exist on newer archs such as aarch64. This leads the build to break on aarch64 hosts with error: error: 'SYS_getdents' was not declared in this scope Change-Id: I8701fb5b61c0418b14a9463ef135a391a7f7a9ba Reviewed-on: https://gem5-review.googlesource.com/c/14596 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-11-27systemc: set endianess to fix build for ARM hostCiro Santilli
ARM architectures were not covered in the endianess #if cases, which lead the build to fail on an arm host with message: error The file boost/detail/endian.hpp needs to be set up for your CPU type. Change-Id: Id012cf37810da113174a51746e290e25138739cb Reviewed-on: https://gem5-review.googlesource.com/c/14595 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-27base: Add some functions to convert floats to bits and vice versa.Gabe Black
These make it easier to extract the binary representation of floats and doubles, and given a binary representation convert it back again. The versions with a size prefix are safer to use since they make it clear what size inputs/outputs are expected. The versions without are to make writing generic code easier in case the same code snippet, templated function, etc., needs to be applied in both circumstances. Change-Id: Ib1f35a7e88e00806a7c639c211c5699b4af5a472 Reviewed-on: https://gem5-review.googlesource.com/c/14455 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-26mem-cache: Add setters to validate and secure blockDaniel R. Carvalho
In order to allow polymorphism of the block these two functions have been added, and all direct status assignments to these bits have been substituted. We also assert that the block has been invalidated before insertion. Then the block is validated in the insertion. Change-Id: Ie7be42408721ad4c2c9dc880f82a62cb594f8668 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/14362 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-22cpu: Made LTAGE parameters configurablePau Cabre
This includes TAGE tag sizes, TAGE table sizes, U counters reset period, loop predictor associativity, path history size, the USE_ALT_ON_NA size and the WITHLOOP size Change-Id: I935823f0a5794f5d55b744263798897a813dc1bd Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14417 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-22cpu: Fixed useful counter handling in LTAGEPau Cabre
Increased to 2 bits of useful counter per TAGE entry as described in the LTAGE paper (and made the size configurable) Changed how the useful counters are incremented/decremented as described in the LTAGE paper Change-Id: I8c692cc7c180d29897cb77781681ff498a1d16c8 Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14215 Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-22cpu: Fixes on the loop predictor part of LTAGEPau Cabre
Fixed the following fields of the loop predictor entries as described on the LTAGE paper: - Age counter (it was 3 bits and it should be 8 bits) - Tag (it was 16 bits and it should be 14 bits). Also some times it used int variables and some times uint16_t, leading to wrong behaviour - Confidence counter (it was 2 bits ins some parts of the code and 3 bits in some other parts. It should be 2 bits) - Iteration counters (they were 16 bits and they should be 14 bits) All the new sizes are now configurable Change-Id: I8884c7454c1e510b65160eb4d5749d3259d34096 Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14216 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-21x86: Get rid of a problematic DPRINTF in PremFp.Gabe Black
This DPRINTF shouldn't be necessary since it shows the operands and results of the instruction which the trace should already make available. Also by passing the destination register to DPRINTF, the ISA parser will assume that it's also a source when tracking dependencies. Change-Id: I820387c82578bdbb8d2e3d91652a6c0185077f54 Reviewed-on: https://gem5-review.googlesource.com/c/14475 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-20sim: Deschedule existing events when destructing an event queue.Gabe Black
Other objects in the simulation may try to deschedule their events when destructed, and if they're cleaned up after the event queue is then they might try to deschedule events on an event queue that no longer exists. Change-Id: I9452ce52fba78297ce3dc4b3884289b5e2f2574d Reviewed-on: https://gem5-review.googlesource.com/c/14400 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-19base: Don't let exceptions leak from the to_number utility function.Gabe Black
This function catches a couple types of exceptions the functions it calls might throw, but if one that it doesn't catch is thrown, then it will propogate that exception to its own callers, and not initialize the value it was asked to convert. This might be considered desirable behavior since it lets errors propogate and avoids handling them in code that might not know the context of when it's called. On the other hand, it upsets g++ since it thinks that there might be an uninitialized value used elsewhere, even though that value will only be uninitialized if an exception is propogating, and the code that would use it is after a point where that exception would have been caught and execution would have resumed. To satisfy g++ and to also avoid silently hiding errors, this change adds a catch all which will panic if an unexpected exception is raised. Change-Id: Ie94dcef3a50f7902566328a3fa2eac59b3cf9aad Reviewed-on: https://gem5-review.googlesource.com/c/14399 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-19systemc: Stop explicitly adding the systemc ext dir to CPPPATH.Gabe Black
That's now handled automatically when the native systemc API is enabled. Change-Id: If1f88929af335a40554a9fd8df6f68aa1a4c0ba4 Reviewed-on: https://gem5-review.googlesource.com/c/14398 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-19systemc: Put systemc headers in the include path when supported.Gabe Black
When the native systemc API support is built in, put the systemc and systemc.h header files in the include path so they can be used as normal. We don't want any external systemc headers being included and getting mixed in with our local ones. Change-Id: I5fc01ff5f069cfadb7c19a9dead13e7ce7272976 Reviewed-on: https://gem5-review.googlesource.com/c/14397 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-19systemc: Increase the stack size for the sc_main fiber to 8MB.Gabe Black
This is a reasonable size for a stack, and the default size for a stack on Linux as determined by some quick Googling. The sc_main fiber would normally use the primary program stack if run under the standard systemc implementation, and so might expect to have more room to play with. Change-Id: Ie12344939e7b249da203630ebc7dc773a387d716 Reviewed-on: https://gem5-review.googlesource.com/c/14396 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-18base: Set up a guard page for fiber stacks.Gabe Black
This will help detect stack overflow for fibers. Change-Id: Iff2b102120ec351709e495291d6bead597f8d10c Reviewed-on: https://gem5-review.googlesource.com/c/14395 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-18mem-cache: a missing cast was truncating addressesJavier Bueno
High bits were truncated when computing the block address Change-Id: Iab2a4c6063ece2d1d4c24ce5686045a6d6d35434 Reviewed-on: https://gem5-review.googlesource.com/c/14415 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-17cpu: Fix LTAGE max number of allocations on updatePau Cabre
The LTAGE paper states that only one TAGE entry can be allocated when updating Change-Id: I6cfb4d80ce835e93d4bf5099ef88a7d425abaddd Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14195 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-17configs: Added an option for choosing branch predictor typePau Cabre
Added the parameter "--bp-type" to set the branch predictor type Added the parameter "--list-bp-types" to list all the available branch predictor types Change-Id: Ia6aae90c784aef359b6d8233c8383cd7a871aca1 Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14015 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-16sim: Fix data type of ticks per second before passing it to C++Srikant Bharadwaj
Casts ticks per second value to int before passing it to C++. Python throws an error because of incompatible type because of the recent change. Change-Id: Ibcaf8c327f1be0dba38763975d389584addd8373 Reviewed-on: https://gem5-review.googlesource.com/c/14375 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-16mem: avoid calling regStat twice on a QoSPolicyMatteo Andreozzi
Change-Id: I216c57073fabe29c3f898a5d89cee41efd4277d5 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13696 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-16cpu: Fix the usage of const DynInstPtrRekai Gonzalez-Alberquilla
Summary: Usage of const DynInstPtr& when possible and introduction of move operators to RefCountingPtr. In many places, scoped references to dynamic instructions do a copy of the DynInstPtr when a reference would do. This is detrimental to performance. On top of that, in case there is a need for reference tracking for debugging, the redundant copies make the process much more painful than it already is. Also, from the theoretical point of view, a function/method that defines a convenience name to access an instruction should not be considered an owner of the data, i.e., doing a copy and not a reference is not justified. On a related topic, C++11 introduces move semantics, and those are useful when, for example, there is a class modelling a HW structure that contains a list, and has a getHeadOfList function, to prevent doing a copy to an internal variable -> update pointer, remove from the list -> update pointer, return value making a copy to the assined variable -> update pointer, destroy the returned value -> update pointer. Change-Id: I3bb46c20ef23b6873b469fd22befb251ac44d2f6 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13105 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-15mem-cache: fix invalid iterator accessJavier Bueno
An iterator was assigned end() and then it was used to access its corresponding element. Change-Id: I87246cf56cbc694dd6b4e2cabbe84a08429d2ac3 Reviewed-on: https://gem5-review.googlesource.com/c/14361 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-15mem-cache: Make StridePrefetcher use Replacement PoliciesDaniel
Previously StridePrefetcher was only able to use random replacement policy. This change allows all replacement policies to be applied to the pc table. Change-Id: I8714e71a6a4c9c31fbca49a07a456dcacd3e402c Signed-off-by: Daniel <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/14360 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-15mem-cache: Add invalidation function to StrideEntryDaniel
Add invalidation function to StrideEntry so that every entry can be invalidated appropriately. Change-Id: I38c42b7d7c93d839f797d116f1d2c88572123c0e Signed-off-by: Daniel <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/14359 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-15mem-cache: Make PCTable context independentDaniel
Move the unordered_map outside of the PCTable, as it belongs to the StridePrefetcher. By doing so we are moving towards a table that ressembles the ones of the Tags classes. Some functions have been moved from the prefetcher to the PCTable, as they didn't belong there. As such, they have been renamed to remove the unnecessary prefix. Change-Id: I3e54bc7dee65e1f78d96b0d548ac8345b7bd4364 Signed-off-by: Daniel <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/14358 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-15mem-cache: Vectorize StridePrefetcher's entries.Daniel
Turn StridePrefetcher::PCTable::entries into a vector of vectors. Change-Id: I2a4589a76eb205910c43723638b7989eddd5ca24 Reviewed-on: https://gem5-review.googlesource.com/c/14357 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-15mem-cache: Return entry in StridePrefetcher::pcTableHit()Daniel
Return a pointer to the entry instead of returning a boolean and passing a pointer reference. As a side effect, change the name of the function to be more descriptive of the functionality. Change-Id: Iad44979e98031754c1d0857b1790c0eaf77e9765 Signed-off-by: Daniel <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/14356 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-15mem-cache: Cleanup prefetchersDaniel
Prefetcher code had extra variables, dependencies that could be removed, code duplication, and missing overrides. Change-Id: I6e9fbf67a0bdab7eb591893039e088261f52d31a Signed-off-by: Daniel <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/14355 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-14cpu: Fixed ratio of pred to hyst bits for LTAGE BimodalPau Cabre
The LTAGE paper states 1 hyst bit shared for 4 pred bits. Made this ratio configurable use 4 by default. Also changed the Bimodal structure to use two std::vector<bool> (one for pred and one for hyst bits) Change-Id: I6793e8e358be01b75b8fd181ddad50f259862d79 Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14120 Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com> Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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