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2015-12-10dev: Move existing PCI device functionality to src/dev/pciAndreas Sandberg
Move pcidev.(hh|cc) to src/dev/pci/device.(hh|cc) and update existing devices to use the new header location. This also renames the PCIDEV debug flag to have a capitalization that is consistent with the PCI host and other devices. --HG-- rename : src/dev/Pci.py => src/dev/pci/PciDevice.py rename : src/dev/pcidev.cc => src/dev/pci/device.cc rename : src/dev/pcidev.hh => src/dev/pci/device.hh rename : src/dev/pcireg.h => src/dev/pci/pcireg.h
2015-11-05sim: Disable gzip compression for writefile pseudo instructionSascha Bischoff
The writefile pseudo instruction uses OutputDirectory::create and OutputDirectory::openFile to create the output files. However, by default these will check the file extention for .gz, and create a gzip compressed stream if the file ending matches. When writing out files, we want to write them out exactly as they are in the guest simulation, and never want to compress them with gzio. Additionally, this causes m5 writefile to fail when checking the error flags for the output steam. With this patch we add an additional no_gz argument to OutputDirectory::create and OutputDirectory::openFile which allows us to override the gzip compression. Therefore, for m5 writefile we disable the filename check, and always create a standard ostream.
2015-09-18dev, arm: Add gem5 extensions to support more than 8 coresKarthik Sangaiah
Previous ARM-based simulations were limited to 8 cores due to limitations in GICv2 and earlier. This changeset adds a set of gem5-specific extensions that enable support for up to 256 cores. When the gem5 extensions are enabled, the GIC uses CPU IDs instead of a CPU bitmask in the GIC's register interface. To OS can enable the extensions by setting bit 0x200 in ICDICTR. This changeset is based on previous work by Matt Evans.
2015-12-09mem: remove acq/rel cmds from packet and add mem fence reqTony Gutierrez
2015-12-09syscall_emul: don't check host fd when allocating target fdSteve Reinhardt
There's a well-meaning check in Process::allocFD() to return an invalid target fd (-1) if the incoming host fd is -1. However, this means that emulated drivers, which want to allocate a target fd that doesn't correspond to a host fd, can't use -1 to indicate an intentionally invalid host fd. It turns out the allocFD() check is redundant, as callers always test the host fd for validity before calling. Also, callers never test the return value of allocFD() for validity, so even if the test failed, it would likely have the undesirable result of returning -1 to the target app as a file descriptor without setting errno. Thus the check is pointless and is now getting in the way, so it seems we should just get rid of it.
2015-12-07cpu: Support virtual addr in elastic tracesRadhika Jagtap
This patch adds support to optionally capture the virtual address and asid for load/store instructions in the elastic traces. If they are present in the traces, Trace CPU will set those fields of the request during replay.
2015-12-07cpu: Create record type enum for elastic tracesRadhika Jagtap
This patch replaces the booleans that specified the elastic trace record type with an enum type. The source of change is the proto message for elastic trace where the enum is introduced. The struct definitions in the elastic trace probe listener as well as the Trace CPU replace the boleans with the proto message enum. The patch does not impact functionality, but traces are not compatible with previous version. This is preparation for adding new types of records in subsequent patches.
2015-12-07cpu: Add TraceCPU to playback elastic tracesRadhika Jagtap
This patch defines a TraceCPU that replays trace generated using the elastic trace probe attached to the O3 CPU model. The elastic trace is an execution trace with data dependencies and ordering dependencies annoted to it. It also replays fixed timestamp instruction fetch trace that is also generated by the elastic trace probe. The TraceCPU inherits from BaseCPU as a result of which some methods need to be defined. It has two port subclasses inherited from MasterPort for instruction and data ports. It issues the memory requests deducing the timing from the trace and without performing real execution of micro-ops. As soon as the last dependency for an instruction is complete, its computational delay, also provided in the input trace is added. The dependency-free nodes are maintained in a list, called 'ReadyList', ordered by ready time. Instructions which depend on load stall until the responses for read requests are received thus achieving elastic replay. If the dependency is not found when adding a new node, it is assumed complete. Thus, if this node is found to be completely dependency-free its issue time is calculated and it is added to the ready list immediately. This is encapsulated in the subclass ElasticDataGen. If ready nodes are issued in an unconstrained way there can be more nodes outstanding which results in divergence in timing compared to the O3CPU. Therefore, the Trace CPU also models hardware resources. A sub-class to model hardware resources is added which contains the maximum sizes of load buffer, store buffer and ROB. If resources are not available, the node is not issued. The 'depFreeQueue' structure holds nodes that are pending issue. Modeling the ROB size in the Trace CPU as a resource limitation is arguably the most important parameter of all resources. The ROB occupancy is estimated using the newly added field 'robNum'. We need to use ROB number as sequence number is at times much higher due to squashing and trace replay is focused on correct path modeling. A map called 'inFlightNodes' is added to track nodes that are not only in the readyList but also load nodes that are executed (and thus removed from readyList) but are not complete. ReadyList handles what and when to execute next node while the inFlightNodes is used for resource modelling. The oldest ROB number is updated when any node occupies the ROB or when an entry in the ROB is released. The ROB occupancy is equal to the difference in the ROB number of the newly dependency-free node and the oldest ROB number in flight. If no node dependends on a non load/store node then there is no reason to track it in the dependency graph. We filter out such nodes but count them and add a weight field to the subsequent node that we do include in the trace. The weight field is used to model ROB occupancy during replay. The depFreeQueue is chosen to be FIFO so that child nodes which are in program order get pushed into it in that order and thus issued in the in program order, like in the O3CPU. This is also why the dependents is made a sequential container, std::set to std::vector. We only check head of the depFreeQueue as nodes are issued in order and blocking on head models that better than looping the entire queue. An alternative choice would be to inspect top N pending nodes where N is the issue-width. This is left for future as the timing correlation looks good as it is. At the start of an execution event, first we attempt to issue such pending nodes by checking if appropriate resources have become available. If yes, we compute the execute tick with respect to the time then. Then we proceed to complete nodes from the readyList. When a read response is received, sometimes a dependency on it that was supposed to be released when it was issued is still not released. This occurs because the dependent gets added to the graph after the read was sent. So the check is made less strict and the dependency is marked complete on read response instead of insisting that it should have been removed on read sent. There is a check for requests spanning two cache lines as this condition triggers an assert fail in the L1 cache. If it does then truncate the size to access only until the end of that line and ignore the remainder. Strictly-ordered requests are skipped and the dependencies on such requests are handled by simply marking them complete immediately. The simulated seconds can be calculated as the difference between the final_tick stat and the tickOffset stat. A CountedExitEvent that contains a static int belonging to the Trace CPU class as a down counter is used to implement multi Trace CPU simulation exit.
2015-12-07mem: Add instruction sequence number to requestRadhika Jagtap
This patch adds the instruction sequence number to the request and provides a request constructor that accepts a sequence number for initialization.
2015-12-07proto, probe: Add elastic trace probe to o3 cpuRadhika Jagtap
The elastic trace is a type of probe listener and listens to probe points in multiple stages of the O3CPU. The notify method is called on a probe point typically when an instruction successfully progresses through that stage. As different listener methods mapped to the different probe points execute, relevant information about the instruction, e.g. timestamps and register accesses, are captured and stored in temporary InstExecInfo class objects. When the instruction progresses through the commit stage, the timing and the dependency information about the instruction is finalised and encapsulated in a struct called TraceInfo. TraceInfo objects are collected in a list instead of writing them out to the trace file one a time. This is required as the trace is processed in chunks to evaluate order dependencies and computational delay in case an instruction does not have any register dependencies. By this we achieve a simpler algorithm during replay because every record in the trace can be hooked onto a record in its past. The instruction dependency trace is written out as a protobuf format file. A second trace containing fetch requests at absolute timestamps is written to a separate protobuf format file. If the instruction is not executed then it is not added to the trace. The code checks if the instruction had a fault, if it predicated false and thus previous register values were restored or if it was a load/store that did not have a request (e.g. when the size of the request is zero). In all these cases the instruction is set as executed by the Execute stage and is picked up by the commit probe listener. But a request is not issued and registers are not written. So practically, skipping these should not hurt the dependency modelling. If squashing results in squashing younger instructions, it may happen that the squash probe discards the inst and removes it from the temporary store but execute stage deals with the instruction in the next cycle which results in the execute probe seeing this inst as 'new' inst. A sequence number of the last processed trace record is used to trap these cases and not add to the temporary store. The elastic instruction trace and fetch request trace can be read in and played back by the TraceCPU.
2015-12-07probe: Add probe in Fetch, IEW, Rename and CommitRadhika Jagtap
This patch adds probe points in Fetch, IEW, Rename and Commit stages as follows. A probe point is added in the Fetch stage for probing when a fetch request is sent. Notify is fired on the probe point when a request is sent succesfully in the first attempt as well as on a retry attempt. Probe points are added in the IEW stage when an instruction begins to execute and when execution is complete. This points can be used for monitoring the execution time of an instruction. Probe points are added in the Rename stage to probe renaming of source and destination registers and when there is squashing. These probe points can be used to track register dependencies and remove when there is squashing. A probe point for squashing is added in Commit to probe squashed instructions.
2015-12-05dev: Rewrite PCI host functionalityAndreas Sandberg
The gem5's current PCI host functionality is very ad hoc. The current implementations require PCI devices to be hooked up to the configuration space via a separate configuration port. Devices query the platform to get their config-space address range. Un-mapped parts of the config space are intercepted using the XBar's default port mechanism and a magic catch-all device (PciConfigAll). This changeset redesigns the PCI host functionality to improve code reuse and make config-space and interrupt mapping more transparent. Existing platform code has been updated to use the new PCI host and configured to stay backwards compatible (i.e., no guest-side visible changes). The current implementation does not expose any new functionality, but it can easily be extended with features such as automatic interrupt mapping. PCI devices now register themselves with a PCI host controller. The host controller interface is defined in the abstract base class PciHost. Registration is done by PciHost::registerDevice() which takes the device, its bus position (bus/dev/func tuple), and its interrupt pin (INTA-INTC) as a parameter. The registration interface returns a PciHost::DeviceInterface that the PCI device can use to query memory mappings and signal interrupts. The host device manages the entire PCI configuration space. Accesses to devices decoded into the devices bus position and then forwarded to the correct device. Basic PCI host functionality is implemented in the GenericPciHost base class. Most platforms can use this class as a basic PCI controller. It provides the following functionality: * Configurable configuration space decoding. The number of bits dedicated to a device is a prameter, making it possible to support both CAM, ECAM, and legacy mappings. * Basic interrupt mapping using the interruptLine value from a device's configuration space. This behavior is the same as in the old implementation. More advanced controllers can override the interrupt mapping method to dynamically assign host interrupts to PCI devices. * Simple (base + addr) remapping from the PCI bus's address space to physical addresses for PIO, memory, and DMA.
2015-12-04cpu: fix unitialized variable which may cause assertion failurePau Cabre
The assert in lsq_unit_impl.hh line 963 needs pktPending to be initialized to NULL (I got the assertion failure several times without the fix). Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-12-04sim: Get rid of the non-const serialize() methodAndreas Sandberg
The last SimObject using the legacy serialize API with non-const methods has now been transitioned to the new API. This changeset removes the serializeOld() methods from the serialization base class as they are no longer used.
2015-12-04arm, config: Automatically discover available platformsAndreas Sandberg
Add support for automatically discover available platforms. The Python-side uses functionality similar to what we use when auto-detecting available CPU models. The machine IDs have been updated to match the platform configurations. If there isn't a matching machine ID, the configuration scripts default to -1 which Linux uses for device tree only platforms.
2015-12-04dev, arm: Disable R/B swap in HDLCD by defaultAndreas Sandberg
The HDLCD model implements a workaround that swaps the red and blue channels. This works around an issue in certain old kernels. The new driver doesn't seem to have this behavior, so disable the workaround by default and enable it in the affected platforms.
2015-12-04dev, arm: Split MCC and DCC subsystemsAndreas Sandberg
Devices behind the Versatile Express configuration controllers are currently all lumped into one SimObject. This will make DTB generation challenging since the DTB assumes them to be in different parts of the hierarchy. It also makes it hard to model other CoreTiles without also replicating devices from the motherboard. This changeset splits the VExpressCoreTileCtrl into two subsystems: VExpressMCC for all motherboard-related devices and CoreTile2A15DCC for Core Tile specific devices.
2015-12-04sim: Add support for generating back traces on errorsAndreas Sandberg
Add functionality to generate a back trace if gem5 crashes (SIGABRT or SIGSEGV). The current implementation uses glibc's stack traversal support if available and stubs out the call to print_backtrace() otherwise.
2015-12-03arm: Add support for automatic boot loader selectionAndreas Sandberg
Add support for automatically selecting a boot loader that matches the guest system's kernel. Instead of accepting a single boot loader, the ArmSystem class now accepts a vector of boot loaders. When initializing a system, the we now look for the first boot loader with an architecture that matches the kernel. This changeset makes it possible to use the same system for both 64-bit and 32-bit kernels.
2015-12-03dev, mips: Remove the unused MaltaPChip classAndreas Sandberg
The MaltaPChip class is currently unused and identical (except for the class name) to the TsunamiPChip. If someone decides to implement PCI for Malta, they should make sure to share code with the Tsunami implementation if they are similar.
2015-12-01config: Fix broken SimObject listingAndreas Sandberg
The gem5 option '--list-sim-objects' is supposed to list all available SimObjects and their parameters. It currently chokes on SimObjects with parameters that have an object instance as their default value. This is caused by __str__ in SimObject trying to resolve its complete path. When the path resolution method reaches the parent object (a MetaSimObject since it hasn't been instantiated), it dies with a Python exception. This changeset adds a guard to stop path resolution if the parent object is a MetaSimObject.
2015-11-24dev: Remove unnecessary header includeAndreas Sandberg
--HG-- extra : rebase_source : 64046371962e98413757bc3ab0c0d48dfb11ff1e
2015-11-25mem: Fix search-replace issues in DRAMPower wrapper licenseAndreas Hansson
Fix a number of unintentional insertions of 'const'.
2015-11-22config: Added missing types to JSON/INI Python readerAndrew Bardsley
Added the missing types EthernetAddr and Current to the JSON/INI file reader example configs/example/read_config.py. Also added __str__ to EthernetAddr to make values appear in the same form in JSON an INI files.
2015-11-22arm, dev: Fix flash model serialization code typosGeoffrey Blake
The flash model has typos in its serialization code for unknownPages, locationTable, blockValidEntries, and blockEmptyEntries arrays where it would save each entry in the array under the same name in the checkpoint. This patch fixes these typos.
2015-11-22cpu: Fix base FP and CC register index in o3 insertThread()Nathanael Premillieu
Note that the method is not used, and could possibly be deleted.
2015-11-22arm: Fix fplib 128-bit shift operatorsNathanael Premillieu
Appease clang.
2015-11-22cpu: Fix memory leak in traffic generatorAndreas Hansson
In cases where we discard the packet, make sure to also delete it and the associated request.
2015-11-20cpu: Enforce 1 interrupt controller per threadAndreas Sandberg
Consider it a fatal configuration error if the number of interrupt controllers doesn't match the number of threads in an SMT configuration.
2015-11-16Merged changesets: 47e2adf7fb1a and b65d4e878ed2Nilay Vaish
--HG-- extra : amend_source : c51de9ae5387aba6fae8403677054678beceb2ab
2015-11-16x86: Invalidating TLB entry on page faultSwapnil Haria
As per the x86 architecture specification, matching TLB entries need to be invalidated on a page fault. For instance, after a page fault due to inadequate protection bits on a TLB hit, the TLB entry needs to be invalidated. This behavior is clearly specified in the x86 architecture manuals from both AMD and Intel. This invalidation is missing currently in gem5, due to which linux kernel versions 3.8 and up cannot be simulated efficiently. This is exposed by a linux optimisation in commit e4a1cc56e4d728eb87072c71c07581524e5160b1, which removes a tlb flush on updating page table entries in x86. Testing: Linux kernel versions 3.8 onwards were booting very slowly in FS mode, due to repeated page faults (~300000 before the first print statement in a bash file). Ensured that page fault rate drops drastically and observed reduction in boot time from order of hours to minutes for linux kernel v3.8 and v3.11
2015-11-16x86: cpuid: add family to warn() messageBjoern A. Zeeb
doCpuid() has to identical warn messages about unimplemented functions. Add the family to the log message to make them distinguishable. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-11-16x86: pagetable walker: fix typo in commentBjoern A. Zeeb
2015-11-16sparc: Make remote debugging with gdb workPalle Lyckegaard
Remove sparc V8 TBR register from list of registers since it is not part of sparc V9. This brings the number of registers in sync with what gdb expects Without this patch gdb complains about receoved packet too long. with this patch gdb is able to work properly with gem5 for remote debugging. Note: gdb is version 7.8 Note: gdb is configured with --target=sparc64-sun-solaris2.8 Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-11-16o3: drop unused statistic wbPenalized and wbPenalizedRateNilay Vaish
2015-11-15arm: Add missing explicit overrides for classic cachesAndreas Sandberg
Make clang when compiling on OSX.
2015-07-20ruby: added stl vector of ints to be used by SLICCBrad Beckmann
2015-11-13slicc: fixes for the Address to Addr changeset (11025)Tony Gutierrez
misc changes now that Address has become Addr including int to address util function
2015-11-13ruby: add BoolVecJoe Gross
The BoolVec typedef and insertion operator overload function simplify usage of vectors of type bool
2015-07-20mem: add boolean to disable PacketQueue's size sanity checkBrad Beckmann
the sanity check, while generally useful for exposing memory system bugs, may be spurious with respect to GPU workloads, which may generate many more requests than typical CPU workloads. the large number of requests generated by the GPU may cause the req/resp queues to back up, thus queueing more than 100 packets.
2015-11-11dev, arm: Initialized the iccrpr register in the GICAndreas Sandberg
The IICRPR register in the GIC is currently not being initialized when the GIC is instantiated. Initialize to the value mandated by the architecture specification.
2015-11-05dev: Add basic checkpoint support to VirtIO9PProxy deviceSascha Bischoff
This patch adds very basic checkpoint support for the VirtIO9PProxy device. Previously, attempts to checkpoint gem5 with a present 9P device caused gem5 to fatal as none of the state is tracked. We still do not track any state, but we replace the fatal with a warning which is triggered if the device has been used by the guest system. In the event that it has not been used, we assume that no state is lost during checkpointing. The warning is triggered on both a serialize and an unserialize to ensure maximum visibility for the user.
2015-11-09dev: Remove unused header includesAndreas Sandberg
Devices should never need to include dev/pciconfall.hh. --HG-- extra : amend_source : 3a6e56485d432b49e2af22407982fa785c0ccb68
2015-11-09dev: Don't access the platform directly in PCI devicesAndreas Sandberg
Cleanup PCI devices to avoid using the PciDevice::platform pointer directly. The PCI-specific functionality provided by the Platform should be accessed through the wrappers in PciDevice.
2015-11-06mem: Add an option to perform clean writebacks from cachesAndreas Hansson
This patch adds the necessary commands and cache functionality to allow clean writebacks. This functionality is crucial, especially when having exclusive (victim) caches. For example, if read-only L1 instruction caches are not sending clean writebacks, there will never be any spills from the L1 to the L2. At the moment the cache model defaults to not sending clean writebacks, and this should possibly be re-evaluated. The implementation of clean writebacks relies on a new packet command WritebackClean, which acts much like a Writeback (renamed WritebackDirty), and also much like a CleanEvict. On eviction of a clean block the cache either sends a clean evict, or a clean writeback, and if any copies are still cached upstream the clean evict/writeback is dropped. Similarly, if a clean evict/writeback reaches a cache where there are outstanding MSHRs for the block, the packet is dropped. In the typical case though, the clean writeback allocates a block in the downstream cache, and marks it writable if the evicted block was writable. The patch changes the O3_ARM_v7a L1 cache configuration and the default L1 caches in config/common/Caches.py
2015-11-06mem: Add cache clusivityAndreas Hansson
This patch adds a parameter to control the cache clusivity, that is if the cache is mostly inclusive or exclusive. At the moment there is no intention to support strict policies, and thus the options are: 1) mostly inclusive, or 2) mostly exclusive. The choice of policy guides the behaviuor on a cache fill, and a new helper function, allocOnFill, is created to encapsulate the decision making process. For the timing mode, the decision is annotated on the MSHR on sending out the downstream packet, and in atomic we directly pass the decision to handleFill. We (ab)use the tempBlock in cases where we are not allocating on fill, leaving the rest of the cache unaffected. Simple and effective. This patch also makes it more explicit that multiple caches are allowed to consider a block writable (this is the case also before this patch). That is, for a mostly inclusive cache, multiple caches upstream may also consider the block exclusive. The caches considering the block writable/exclusive all appear along the same path to memory, and from a coherency protocol point of view it works due to the fact that we always snoop upwards in zero time before querying any downstream cache. Note that this patch does not introduce clean writebacks. Thus, for clean lines we are essentially removing a cache level if it is made mostly exclusive. For example, lines from the read-only L1 instruction cache or table-walker cache are always clean, and simply get dropped rather than being passed to the L2. If the L2 is mostly exclusive and does not allocate on fill it will thus never hold the line. A follow on patch adds the clean writebacks. The patch changes the L2 of the O3_ARM_v7a CPU configuration to be mostly exclusive (and stats are affected accordingly).
2015-11-06mem: Avoid unnecessary snoops on writebacks and clean evictionsAli Jafri
This patch optimises the handling of writebacks and clean evictions when using a snoop filter. Instead of snooping into the caches to determine if the block is cached or not, simply set the status based on the snoop-filter result.
2015-11-06mem: Order packet queue only on matching addressesAndreas Hansson
Instead of conservatively enforcing order for all packets, which may negatively impact the simulated-system performance, this patch updates the packet queue such that it only applies the restriction if there are already packets with the same address in the queue. The basic need for the order enforcement is due to coherency interactions where requests/responses to the same cache line must not over-take each other. We rely on the fact that any packet that needs order enforcement will have a block-aligned address. Thus, there is no need for the queue to know about the cacheline size.
2015-11-06mem: Enforce insertion order on the cache response pathAli Jafri
This patch enforces insertion order transmission of packets on the response path in the cache. Note that the logic to enforce order is already present in the packet queue, this patch simply turns it on for queues in the response path. Without this patch, there are corner cases where a request-response is faster than a response-response forwarded through the cache. This violation of queuing order causes problems in the snoop filter leaving it with inaccurate information. This causes assert failures in the snoop filter later on. A follow on patch relaxes the order enforcement in the packet queue to limit the performance impact.
2015-11-06mem: Use the packet delays and do not just zero them outAndreas Hansson
This patch updates the I/O devices, bridge and simple memory to take the packet header and payload delay into account in their latency calculations. In all cases we add the header delay, i.e. the accumulated pipeline delay of any crossbars, and the payload delay needed for deserialisation of any payload. Due to the additional unknown latency contribution, the packet queue of the simple memory is changed to use insertion sorting based on the time stamp. Moreover, since the memory hands out exclusive (non shared) responses, we also need to ensure ordering for reads to the same address.