gem5 - gem5

Age	Commit message (Expand)	Author
2007-08-26	Address translation: Make the page table more flexible.	Gabe Black
2007-08-26	O3 CPU: Remove alignment check from dynamic instruction read/write functions.	Gabe Black
2007-08-26	X86: Remove x86 code that attempted to fix misaligned accesses.	Gabe Black
2007-08-26	Simple CPU: Don't trace instructions that fault. Otherwise they show up twice.	Gabe Black
2007-08-26	Simple CPU: Added code that will split requests that cross block boundaries i...	Gabe Black
2007-08-26	Simple CPU: Make sure only instructions which complete without faulting are c...	Gabe Black
2007-08-26	Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.	Gabe Black
2007-08-26	SPARC: Make sure unaligned access are caught on cached translations as well.	Gabe Black
2007-08-21	Merge with head.	Gabe Black
2007-08-21	o3: Fix for retry ID bug.	Kevin Lim
2007-08-18	Merge with head.	Gabe Black
2007-08-17	Ports: Only try to do EthPort stuff in full system.	Ali Saidi
2007-08-16	PCI: Move PCI Configuration data into devices now that we can inherit paramet...	Ali Saidi
2007-08-16	Devices: Make EtherInts connect in the same way memory ports currently do.	Ali Saidi
2007-08-13	SPARC: Make nops have the IsNop flag set.	Gabe Black
2007-08-13	O3: Set up the predicted npc and nnpc for a fault carrying noop so that it do...	Gabe Black
2007-08-13	SPARC: Move tlb state into the tlb.	Gabe Black
2007-08-13	SPARC: Make the spill and fill handlers use the correct ASI, and let No_Fault...	Gabe Black
2007-08-13	Move the "translate" member functions back into the base o3 class.	Gabe Black
2007-08-13	python: make the DictImporter's unload() work in any context.	Nathan Binkert
2007-08-12	MemorySystem: Fix the use of ?: to produce correct results.	Ali Saidi
2007-08-08	Added fastmem option.	Vincentius Robby
2007-08-08	alpha: Quick fix for things related to TLB MRU cache.	Vincentius Robby
2007-08-10	DMA: Add IOCache and fix bus bridge to optionally only send requests one	Ali Saidi
2007-08-10	Bus: Only call end() on an stl object once in a loop	Ali Saidi
2007-08-08	Port, StaticInst: Revert unnecessary changes.	Vincentius Robby
2007-08-08	alpha: Make the TLB cache to actually work.	Vincentius Robby
2007-08-07	Alpha: Fix an off by one error with the tlb caching mechanism.	Gabe Black
2007-08-07	Merge with head.	Gabe Black
2007-08-07	X86: Added some missing parenthesis in the condition code calculation function.	Gabe Black
2007-08-07	X86: Implemented and hooked in SCAS (scan string)	Gabe Black
2007-08-07	X86: Add a format to handle string instructions which can use the repe and re...	Gabe Black
2007-08-07	X86: Overhaul of ruflags to get it to work correctly.	Gabe Black
2007-08-07	X86: Make a microcode branch microop.	Gabe Black
2007-08-04	Merge with head.	Gabe Black
2007-08-04	X86: Implement microops and instructions that manipulate the flags register.	Gabe Black
2007-08-04	X86: Make 64 bit unaligned accesses work as well as the other sizes.	Gabe Black
2007-08-04	X86: Make the open flags correct.	Gabe Black
2007-08-04	X86: Make fixed register operands ignore register index extensions from the R...	Gabe Black
2007-08-04	X86: Implement the cmpxchg instruction.	Gabe Black
2007-08-04	X86: Start implementing segmentation support.	Gabe Black
2007-08-04	X86: Create a base enum value for indexing into a region of the miscregs.	Gabe Black
2007-08-04	X86: Add the arch_prctl system call and fix up some microcoding.	Gabe Black
2007-08-04	switching: turn on profiling after a switch if there's an event	Nathan Binkert
2007-08-04	switching: Remove the drain and resume code from the switching code.	Nathan Binkert
2007-08-04	python: use the enum values in the memory mode changing code	Nathan Binkert
2007-08-04	swig: %include all of the enums to get all of the definitions.	Nathan Binkert
2007-08-04	python: provide access to stats	Nathan Binkert
2007-08-04	main: return an an exit code of 1 when we exit due to a python exception.	Nathan Binkert
2007-08-04	SimpleCPU: Add some DPRINTFs	Nathan Binkert