| Age | Commit message (Expand) | Author |
|---|
| 2012-04-14 | clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6 | Andreas Hansson |
| 2012-04-13 | SCons: restore Werror option in src/SConscript | Steve Reinhardt |
| 2012-04-12 | Ruby: Ensure order-dependent iteration uses an ordered map | Andreas Hansson |
| 2012-04-09 | tests: Fix building unit tests. | Gabe Black |
| 2012-04-06 | rubytest: remove spurious printf | Brad Beckmann |
| 2012-04-06 | slicc: Controllers attached to Sequencers no longer have to be named L1Cache. | Lisa Hsu |
| 2012-04-06 | sim-ruby: checkpointing fixes and dependent eventq improvements | Brad Beckmann |
| 2012-04-06 | slicc: fixed error message when the type has no inheritance | Brad Beckmann |
| 2012-04-06 | MOESI_hammer: tbe allocation and dependent wakeup fixes | Brad Beckmann |
| 2012-04-06 | python: added __nonzero__ function to SimObject Bool params | Brad Beckmann |
| 2012-04-06 | MOESI_hammer: fixed bug with single cpu + flushes, then modified the regressi... | Brad Beckmann |
| 2012-04-06 | rubytest: seperated read and write ports. | Brad Beckmann |
| 2012-04-06 | MEM: Enable multiple distributed generalized memories | Andreas Hansson |
| 2012-04-05 | NetworkTest: remove unnecessary memory allocation | Tushar Krishna |
| 2012-04-05 | Config: corrects the way Ruby attaches to the DMA ports | Nilay Vaish |
| 2012-04-05 | Python: Make the All proxy traverse SimObject children as well | Andreas Hansson |
| 2012-04-03 | Atomic: Remove the physmem_port and access memory directly | Andreas Hansson |
| 2012-03-31 | X86: Fix address size handling so real mode works properly. | Gabe Black |
| 2012-03-30 | MEM: Remove legacy DRAM in preparation for memory updates | Andreas Hansson |
| 2012-03-30 | Ruby: Remove the physMemPort and instead access memory directly | Andreas Hansson |
| 2012-03-30 | MEM: Introduce the master/slave port sub-classes in C++ | William Wang |
| 2012-03-30 | CPU: Unify initMemProxies across CPUs and simulation modes | Andreas Hansson |
| 2012-03-26 | range_map: Enable const find and iteration | Andreas Hansson |
| 2012-03-26 | Power: Change bitfield name to avoid conflicts with range_map | Andreas Hansson |
| 2012-03-23 | Ruby: Fix Set::print for 32-bit hosts | Andreas Hansson |
| 2012-03-22 | MEM: Unify bus access methods and prepare for master/slave split | Andreas Hansson |
| 2012-03-22 | MEM: Split SimpleTimingPort into PacketQueue and ports | Andreas Hansson |
| 2012-03-22 | Scons: Remove Werror=False in SConscript files | Andreas Hansson |
| 2012-03-21 | Python: Fix a conditional expression that requires Python 2.5 | Andreas Hansson |
| 2012-03-21 | ARM: Fix case where cond/uncond control is mis-specified | Nathanael Premillieu |
| 2012-03-21 | ARM: Clean up condCodes in IT blocks. | Ali Saidi |
| 2012-03-21 | ARM: IT doesn't need to be serializing. | Geoffrey Blake |
| 2012-03-21 | O3: Fix sizing of decode to rename skid buffer. | Andrew Lukefahr |
| 2012-03-21 | ARM: Add RTC to PBX System | Koan-Sin Tan |
| 2012-03-21 | O3: Fix size of skid buffer between fetch and decode when widths are different | Brian Grayson |
| 2012-03-21 | ARM: Fix uninitialized value in ARM RTC model. | Ali Saidi |
| 2012-03-19 | Garnet: Stats at vnet granularity + code cleanup | Tushar Krishna |
| 2012-03-19 | gcc: Clean-up of non-C++0x compliant code, first steps | Andreas Hansson |
| 2012-03-19 | clang: Fix recently introduced clang compilation errors | Andreas Hansson |
| 2012-03-19 | scripts: Fix to ensure that port connection count is always set | Andreas Hansson |
| 2012-03-11 | O3: Add fatal when fetchWidth > Impl::MaxWidth. | Brian Grayson |
| 2012-03-09 | ARM: Fix branch prediction issue with CB(N)Z instruction | Brian Grayson |
| 2012-03-09 | O3/Ozone: Eliminate dead code counting software prefetch insts | Geoffrey Blake |
| 2012-03-09 | CheckerCPU: Add function stubs to non-ARM ISA source to compile with CheckerCPU | Geoffrey Blake |
| 2012-03-09 | CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable | Geoffrey Blake |
| 2012-03-09 | ARM: Don't reset CPUs that are going to be switched in. | Ali Saidi |
| 2012-03-09 | System: Move code in initState() back into constructor whenever possible. | Ali Saidi |
| 2012-03-09 | ARM: Fix valgrind reported error on O3 that was causing minor stats changes. | Ali Saidi |
| 2012-03-09 | cache: Allow main memory to be at disjoint address ranges. | Ali Saidi |
| 2012-03-06 | build scripts: Made minor modifications to reduce build overhead time. | Marc Orr |
