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AgeCommit message (Expand)Author
2016-08-12mem: Add snoop filter to SystemXBar by defaultAndreas Hansson
2016-08-12mem: Use FromCache attribute in snoop filter allocationAndreas Hansson
2016-08-12mem: Update mostly exclusive policy even furtherAndreas Hansson
2016-08-12mem: Update mostly exclusive cache policy to cover more casesAndreas Hansson
2016-08-12mem: Add a FromCache packet attributeAndreas Hansson
2016-08-10arm, dev: Add support for listing DMA ports in new platformsAndreas Sandberg
2016-08-10ruby: Implement support for functional accesses to PIO rangesAndreas Sandberg
2016-08-10arm: Don't report the boot ROM as a memory in config tablesAndreas Sandberg
2016-08-05sim: fix issues with pwrite(); don't enable fstatfsTony Gutierrez
2016-08-04x86, sim: add some syscalls to X86Tony Gutierrez
2016-08-02arm: s/ctx_id/ctx/ the GICCurtis Dunham
2016-08-02arm: bank GIC registers per CPUCurtis Dunham
2016-08-02arm: refactor page table walkingCurtis Dunham
2016-08-02arm: warn not fail on use of missing miscreg CNTHCTL_EL2Dylan Johnson
2016-08-02arm: Check TLB stage 2 permissions in AArch64Dylan Johnson
2016-08-02arm: correctly assign faulting IPA's to HPFAR_EL2Dylan Johnson
2016-08-02arm: Add TLBI instruction for stage 2 IPA'sDylan Johnson
2016-08-02arm: Fix stage 2 memory attribute checking in AArch64Dylan Johnson
2016-08-02arm: Fix trapping to Hypervisor during MSR/MRS read/writeDylan Johnson
2016-08-02arm: Fix secure state checking in various placesDylan Johnson
2016-08-02arm: Fix stage 2 determination in table walkerDylan Johnson
2016-08-02arm: Refactor aarch64 table walk logic to remove redundancyDylan Johnson
2016-08-02arm: Add check to fault routing for hypervisor/virtualizationDylan Johnson
2016-08-02arm: Fix EL perceived at TLB for address translation instructionsDylan Johnson
2016-08-02arm: Add AArch64 hypervisor call instruction 'hvc'Dylan Johnson
2016-08-02arm: add stage2 translation supportDylan Johnson
2016-08-02arm: enable EL2 supportCurtis Dunham
2016-08-02arm: invalidate TLB miscreg cache on modification of HSCTLRDylan Johnson
2016-08-02arm: change instruction classes to catch hyp trapsDylan Johnson
2016-07-21cpu: Fix Minor SMT WFI/drain interaction issuesMitch Hayenga
2016-07-21cpu: Add SMT support to MinorCPUMitch Hayenga
2016-07-21isa: Modify get/check interrupt routinesMitch Hayenga
2016-07-21base: Add total() to Vector2D statDavid Guillen Fandos
2016-07-21mem: Add snoop traffic statisticDavid Guillen Fandos
2016-07-19dev, dist: Fixed a scheduling bug in the etherswitchMohammad Alian
2016-07-11base: Fix inverted check in ELF .text size warningAndreas Sandberg
2016-07-11arm: Don't consult the TLB test iface for functional translationsAndreas Sandberg
2016-07-11base: Convert ELF .text size check assertion to a warningAndreas Sandberg
2016-07-11mem: Remove stale argument from a DPRINTF in the cache codeNikos Nikoleris
2016-07-01ruby: Fix double statistic registration in garnetMatthew Poremba
2016-07-01ext: Update DRAMPowerMatthias Jung
2016-07-01mem: different HMC configurationAbdul Mutaal Ahmad
2016-06-28scons: Track swig packages when loading embedded swig codeAndreas Hansson
2016-06-20arm: Mark uninitialized new TLB entries as not validNikos Nikoleris
2016-06-20sim: Added library include to fix build errors on clang-703.0.31Reiley Jeapaul
2016-06-20mem: Fix the snoop filter when there is a downstream addr mapperNikos Nikoleris
2016-06-20mem: Resolve TrafficGen trace relative to the configAndreas Sandberg
2016-06-20kern, arm: Dump dmesg on kernel panic/oopsAndreas Sandberg
2016-06-20base: Fix multiple names to one address bug in SymbolTableAndreas Sandberg
2016-06-18gpu-compute: Fixed a bug in decoding Atomic STTuan Ta
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