Age | Commit message (Collapse) | Author |
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into zeep.pool:/z/saidi/work/m5.newmem
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matter). Otherwise, when you turn on debugprintf alters the execution
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though I don't believe that's true. Placate it anyway.
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/head
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into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/head
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src/cpu/o3/cpu.cc:
Use proper cycles for these equations.
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not a cpp file because c99
(which defines fenv) doesn't necessarily extend to c++ and it is a problem with solaris. If really
desired this could wrap the ieeefp interface found in bsd* as well, but I see no need at the moment.
src/arch/alpha/isa/fp.isa:
src/arch/sparc/isa/formats/basic.isa:
use m5_fesetround()/m5_fegetround() istead of fenv interface directly
src/arch/sparc/isa/includes.isa:
use base/fenv instead of fenv directly
src/base/SConscript:
add fenv to sconscript
src/base/fenv.hh:
src/base/random.cc:
m5 implementation to standerdize fenv across platforms.
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encumbered directory
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they're used
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/head
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03cpu yet.
src/cpu/simple/base.cc:
Cpu's should start as unallocated, not suspended
src/cpu/simple_thread.cc:
Wait for a thread to be assigned to activate the cpu
src/kern/tru64/tru64.hh:
When looking for a open cpu to assign threads, look for an unallocated one, not a suspended one.
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and python code into m5 to allow swig an python code to
easily added by any SConscript instead of just the one in
src/python. This provides SwigSource and PySource for
adding new files to m5 (similar to Source for C++). Also
provides SimObject for including files that contain SimObject
information and build the m5.objects __init__.py file.
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or automatically do Split(). It isn't used anywhere, and
isn't very consistent with the python features that are
about to be added. Do accept SCons.Node.FS.File arguments
though.
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unproxy() needs to return a new object otherwise all
instances will use the same value. This fix is more
or less unique to NextEthernetAddr because its use of
the proxy stuff is a bit different than everything else.
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to be created
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-spec
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implementations from using doubles to using concatenated singles.
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
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test the stub code for instructions.
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parser as a unit.
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unimplemented instructions in their microcode. This is useful if certain variations of an instruction are implemented, but, for instance, it's memory based versions aren't.
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into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/head
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
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size than the architected one. Also fixed some asserts.
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-spec
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IsStoreConditional flag needs to be set for them because they aren't store conditional instructions, and I should fix the format code which is not handling the opt_flags correctly.
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and added some comments to main.isa
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
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x86-centric stuff.
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seperation between x86 specific parts, and those parts which are implemented in the isa description but could eventually be moved elsewhere.
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rename : src/arch/x86/isa/formats/macroop.isa => src/arch/x86/isa/macroop.isa
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sizes, and sign extend the 32-bit-acting-like-64-bit-immediates.
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-spec
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