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AgeCommit message (Expand)Author
2006-10-28Merge zizzer:/bk/newmemAli Saidi
2006-10-28remove intel nic from SConscriptAli Saidi
2006-10-28This one really needs to be arch/faults.hhGabe Black
2006-10-28Include the right version of faults.hhGabe Black
2006-10-28Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2006-10-28One last adjustment to get rid of skew in the simple atomic cpu.Gabe Black
2006-10-27add packet_access.hhAli Saidi
2006-10-27A more complete attempt to fix the clock skew.Gabe Black
2006-10-27Potential fix to clock skew problem.Gabe Black
2006-10-27Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2006-10-27Got rid of some outdated comments.Gabe Black
2006-10-27Made the regfile compatible with the new definitions in MiscRegFileGabe Black
2006-10-27Clean up MiscRegFileGabe Black
2006-10-26Reorganized the MiscRegFileGabe Black
2006-10-26Cleaned up the decoder slightly.Gabe Black
2006-10-26Added a few functions to stuff values into bitfields in an instruction.Gabe Black
2006-10-26Changed the number of register windows to be more realistic.Gabe Black
2006-10-26Got rid of some debug outputGabe Black
2006-10-26Change the default function from setMiscRegWithEffect to setMiscRegGabe Black
2006-10-26Merge zizzer:/bk/newmemAli Saidi
2006-10-25Fix simple timing port keep a list of all packets, have only one event, and s...Ali Saidi
2006-10-25Fixed the priv instruction format.Gabe Black
2006-10-25Implemented the saved and restored instructions, fixed up register window ins...Gabe Black
2006-10-25Fixed the bitfield FCN to include the right bits.Gabe Black
2006-10-25Implemented the SPARC fill and spill handlers.Gabe Black
2006-10-25Fix fixPacket functionality to calculate sizes properlyRon Dreslinski
2006-10-24Replace the Alpha No op with a SPARC one.Gabe Black
2006-10-24Merge zizzer:/bk/newmemAli Saidi
2006-10-24Add more traceflags for ethernetAli Saidi
2006-10-24Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemSteve Reinhardt
2006-10-23Merge zizzer:/bk/newmemLisa Hsu
2006-10-23get rid of the "resume" step at the end of changeToTiming/Atomic because this...Lisa Hsu
2006-10-23make this parallel to the other cpu types so that resume works correctly.Lisa Hsu
2006-10-23Minor compile fix. Not sure why this is broken.Gabe Black
2006-10-23Move around more SPARC memory code, and make block memory operations work wit...Gabe Black
2006-10-23Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2006-10-23Broke Load/Store instructions into microcode, and partially refactored memory...Gabe Black
2006-10-23Don't let interupts interupt microcode at undesired points.Gabe Black
2006-10-23Files in base shouldn't depend on things in sim. Changed "sim/host.hh" to <in...Gabe Black
2006-10-23Start making memory ops work with InitiateAcc and CompleteAcc, and some minor...Gabe Black
2006-10-23Change the default constructors to take ExtMachInsts rather than regular Mach...Gabe Black
2006-10-22Clean up cache DPRINTFsSteve Reinhardt
2006-10-22s/pktuest/request/ (all in comments)Steve Reinhardt
2006-10-22Add DPRINTF for non-timed quiesce.Steve Reinhardt
2006-10-21Small bug fixes for timing LL/SC. Better now butSteve Reinhardt
2006-10-21Add Quiesce trace flag to track CPU quiesce/wakeup events.Steve Reinhardt
2006-10-21Just give up if a store conditional misses completelySteve Reinhardt
2006-10-21Fix formatting that got screwed up when tabs were removed.Steve Reinhardt
2006-10-21Refactor coherence state table initialization.Steve Reinhardt
2006-10-21Tweak a few things for better page fault debugging.Steve Reinhardt
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