summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Expand)Author
2015-09-18ruby: print addresses in hexNilay Vaish
2015-09-18ruby: slicc: derive DataMember class from Var instead of PairContainerNilay Vaish
2015-09-17ruby: update WireBuffer API to match that of MessageBufferTony Gutierrez
2015-09-16ruby: Add missing block deallocations in MOESI_hammerLena Olson
2015-09-16ruby: fix message buffer init orderJoe Gross
2015-09-16ruby: message buffer, timer table: significant changesNilay Vaish
2015-09-16ruby: remove unused function removeRequest()Nilay Vaish
2015-09-16ruby: sequencer: remove commented out function printProgress()Nilay Vaish
2015-09-16ruby: rename System.{hh,cc} to RubySystem.{hh,cc}David Hashe
2015-09-16slicc: export uint64_t instead of uint64Anthony Gutierrez
2015-09-15sparc: writing to tick_cmpr should not cause a panicPalle Lyckegaard
2015-09-15dev: IDE Disk: Handle bad IDE image sizeDongxue Zhang
2015-09-15cpu: pred: Local Predictor Reset in Tournament PredictorAndrew Lukefahr
2015-09-15cpu, o3: consider split requests for LSQ checksnoop operationsHongil Yoon
2015-09-14ruby: topology: refactor code.Nilay Vaish
2015-09-14ruby: slicc: remove member buffer_expr from Var classNilay Vaish
2015-09-12merged with 62e1504b9c64Nilay Vaish
2015-09-12ruby: perfect switch: refactor codeNilay Vaish
2015-09-12ruby: simple network: store Switch* in PerfectSwitch and ThrottleNilay Vaish
2015-09-11dev: Add an underrun statistic to the HDLCD controllerAndreas Sandberg
2015-09-11dev, arm: Rewrite the HDLCD controllerAndreas Sandberg
2015-09-08ruby: slicc: remove nextLineHack from Type.pyNilay Vaish
2015-09-05ruby: call setMRU from L1 controllers, not from sequencerNilay Vaish
2015-09-05ruby: adds set and way indices to AbstractCacheEntryNilay Vaish
2015-09-05ruby: set: reimplement using std::bitsetNilay Vaish
2015-09-05ruby: declare all protocol message buffers as parametersNilay Vaish
2015-09-04mem: Avoid setting markPending if not neededAndreas Hansson
2015-09-04mem: Tidy up CacheSetAndreas Hansson
2015-09-04mem: Tidy up the snoop state-transition logicAndreas Hansson
2015-09-04sim: Fix time unit in abort messageAndreas Hansson
2015-09-02sim: tag-based checkpoint versioningCurtis Dunham
2015-09-02sim: support checkpointing std::set<std::string>'sCurtis Dunham
2015-09-02sim: make warning for absent optional parameters optionalCurtis Dunham
2015-09-01ruby: remove random seedNilay Vaish
2015-09-01ruby: directory memory: drop unused variable.Nilay Vaish
2015-09-01sim: Remove broken AutoSerialize support from the event queueAndreas Sandberg
2015-09-01dev: Remove auto-serialization dependency in EtherLinkAndreas Sandberg
2015-09-01sim: Remove autoserialize support for exit eventsAndreas Sandberg
2015-09-01sim: Remove unused SerializeBuilder interfaceAndreas Sandberg
2015-09-01sim: Replace fromInt/fromSimObject with decltypeAndreas Sandberg
2015-09-01sim: Move SimObject resolver to sim_object.hhAndreas Sandberg
2015-08-30ruby: specify number of vnets for each protocolNilay Vaish
2015-08-30ruby: network: drop member m_in_useNilay Vaish
2015-08-30ruby: garnet: mark few functions const in BaseGarnetNetwork.hhNilay Vaish
2015-08-30ruby: slicc: avoid duplicate code for function argument checkNilay Vaish
2015-08-29ruby: eliminate type uint64 and int64Nilay Vaish
2015-08-28ruby: Use the const serialize interface in RubySystemAndreas Sandberg
2015-08-27ruby: handle llsc accesses through CacheEntry, not CacheMemoryNilay Vaish
2015-08-26cpu: quiesce pseudoinsts: Always do full quiesceEmilio Castillo
2015-08-24mem: Revert requirement on packet addr/size always validAndreas Hansson
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 10:26:38 +0000