| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2009-04-26 | X86: Record the initial APIC ID which identifies an APIC in M5. | Gabe Black | |
| The ID as exposed to software can be changed. Tracking those changes in M5 would be cumbersome, especially since there's no guarantee the IDs will remain unique. | |||
| 2009-04-26 | X86, Config: Make makeX86System consider the number of CPUs, and clean up ↵ | Gabe Black | |
| interrupt assignment. | |||
| 2009-04-24 | SPARC: Tighten up the clone system call and SPARCs copyRegs. | Gabe Black | |
| 2009-04-23 | request: reorganize flags to group related flags together. | Steve Reinhardt | |
| 2009-04-23 | X86: Put the StoreCheck flag with the others, and don't collide with other ↵ | Gabe Black | |
| flags. | |||
| 2009-04-22 | stats: expose statistics to python | Nathan Binkert | |
| 2009-04-22 | stats: Move flags into info.hh and use base/flags.hh to manage the flags | Nathan Binkert | |
| 2009-04-22 | stats: Shuffle around info stuff so it can be accessed separately | Nathan Binkert | |
| 2009-04-22 | stats: Rename the info classes to hopefully make things a bit clearer | Nathan Binkert | |
| FooInfoBase became FooInfo FooInfo became FooInfoProxy | |||
| 2009-04-22 | stats: remove simplescalar compatibility for printing | Nathan Binkert | |
| 2009-04-22 | stats: fix initialization bug in distribution text output | Nathan Binkert | |
| 2009-04-22 | i8254xGBe: major style overhaul. | Steve Reinhardt | |
| Moved DescCache template functions from .hh to .cc file. Also fixed lots of line-wrapping problems, and some irregular indentation. | |||
| 2008-07-16 | mem: use single BadAddr responder per system. | Steve Reinhardt | |
| Previously there was one per bus, which caused some coherence problems when more than one decided to respond. Now there is just one on the main memory bus. The default bus responder on all other buses is now the downstream cache's cpu_side port. Caches no longer need to do address range filtering; instead, we just have a simple flag to prevent snoops from propagating to the I/O bus. | |||
| 2009-04-21 | Automated merge with ssh://m5sim.org//repo/m5 | Nathan Binkert | |
| 2009-04-21 | pseudo: only include kernel stats if FULL_SYSTEM. | Nathan Binkert | |
| 2009-04-21 | arm: include missing file for arm | Nathan Binkert | |
| 2009-04-21 | arm: Unify the ARM tlb. We forgot about this when we did the rest. | Nathan Binkert | |
| This code compiles, but there are no tests still | |||
| 2009-04-21 | syscall_emul: style fixes (mostly wrapping overly long lines) | Steve Reinhardt | |
| 2009-04-21 | syscall: Resolve conflicts between m5threads and Gabe's recent SE changes. | Steve Reinhardt | |
| 2009-04-21 | Commit m5threads package. | Daniel Sanchez | |
| This patch adds limited multithreading support in syscall-emulation mode, by using the clone system call. The clone system call works for Alpha, SPARC and x86, and multithreaded applications run correctly in Alpha and SPARC. | |||
| 2009-04-21 | SCons: Export export_vars so SConsopts files can add to them | Nathan Binkert | |
| 2009-04-21 | Minor tweaks for future Ruby compatibility. | Steve Reinhardt | |
| 2009-04-21 | request: add PREFETCH flag. | Steve Reinhardt | |
| 2009-04-20 | request: rename INST_READ to INST_FETCH. | Steve Reinhardt | |
| 2009-04-20 | request: split public and private flags into separate fields. | Steve Reinhardt | |
| This frees up needed space for more public flags. Also: - remove unused Request accessor methods - make Packet use public Request accessors, so it need not be a friend | |||
| 2009-04-19 | Mem: Fill out the comment that describes the LOCKED request flag. | Gabe Black | |
| 2009-04-19 | Mem: Change isLlsc to isLLSC. | Gabe Black | |
| 2009-04-19 | X86: Fix the functions that manipulate large bit arrays in the local APIC. | Gabe Black | |
| 2009-04-19 | X86: Fix up a copyright. | Gabe Black | |
| 2009-04-19 | X86: Fix how the TLB handles the storecheck flag. | Gabe Black | |
| 2009-04-19 | X86: Recognize and handle the lock legacy prefix. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of XADD. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of BTC. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of BTR. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of CMPXCHG. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of BTS. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of DEC. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of INC. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of NEG. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of NOT. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of XCHG. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of XOR. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of SUB. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of AND. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of SBB. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of ADC. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of OR. | Gabe Black | |
| 2009-04-19 | X86: Implement a locking version of ADD. | Gabe Black | |
| 2009-04-19 | X86: Implement the stul microop. | Gabe Black | |
| This microop does a store and unlocks the requested address. The RISC86 microop ISA doesn't seem to have an equivalent to this, so I'm guessing that the store following an ldstl is automatically unlocking. We don't do it this way for performance reasons since the behavior is the same. | |||
| 2009-04-19 | X86: Implement the ldstl microop. | Gabe Black | |
| This microop does a load, checks that a store would succeed, and locks the requested address. | |||
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