| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2009-08-02 | X86: Set up the IDE device correctly, ie. with and using legacy ports. | Gabe Black | |
| 2009-08-02 | IDE: Configure the IDE control to reflect the initial value of the command ↵ | Gabe Black | |
| register. | |||
| 2009-08-02 | X86: Fix the high result of mul1s, and removed undefined shifts from the ↵ | Gabe Black | |
| mult microops. | |||
| 2009-08-01 | Fix setting of INST_FETCH flag for O3 CPU. | Steve Reinhardt | |
| It's still broken in inorder. Also enhance DPRINTFs in cache and physical memory so we can see more easily whether it's getting set or not. | |||
| 2009-08-01 | Clean up some inconsistencies with Request flags. | Steve Reinhardt | |
| 2009-08-01 | Rename internal Request fields to start with '_'. | Steve Reinhardt | |
| The inconsistency was causing a subtle bug with some of the constructors where the params had the same name as the fields. This is also a first step to switching the accessors over to our new "standard", e.g., getVaddr() -> vaddr(). | |||
| 2009-07-31 | merge mips fix and statetrace changes | Korey Sewell | |
| 2009-07-31 | mips: fix ll/sc pairs working incorrectly because of accidental clobber of ↵ | Korey Sewell | |
| LLFLAG | |||
| 2009-07-30 | compile: fix accidental conversion of == into = | Nathan Binkert | |
| 2009-07-29 | ARM: Mul and mla ignore the c and v flags, but we were setting them to 1. | Gabe Black | |
| 2009-07-29 | ARM: Fix an instruction in the cmpxchg kernel provided routine. | Gabe Black | |
| The instruction was encoded as a load instead of the intended store. | |||
| 2009-07-29 | ARM: Get rid of a stray line in the set_tls handler. | Gabe Black | |
| 2009-07-29 | ARM: Make the ARM native tracer stop M5 if control diverges. | Gabe Black | |
| If the control flow of M5's executable and statetrace's target process get out of sync even a little, there will be a LOT of output, very little of which will be useful. There's also almost no hope for recovery. In those cases, we might as well give up and not generate a huge, mostly worthless trace file. | |||
| 2009-07-29 | Simple CPU: Make the simple CPU handle the IntRegs trace flag. | Gabe Black | |
| 2009-07-29 | ARM: Make sure the target process doesn't run away from statetrace. | Gabe Black | |
| 2009-07-29 | ARM: Ignore the "times" system call. | Ali Saidi | |
| 2009-07-29 | ARM: Fix an ioctl constant. | Ali Saidi | |
| 2009-07-27 | ARM: Update some syscall constants and delete others that are Alpha only. | Ali Saidi | |
| 2009-07-27 | ARM: Decode fstmx and fldmx instructions. We can ignore them for now. | Gabe Black | |
| 2009-07-27 | ARM: Only send information that changed between statetrace and M5. | Gabe Black | |
| 2009-07-27 | imported patch nativetracestreamline.patch | Gabe Black | |
| 2009-07-27 | ARM: Make native trace print out what instruction caused an error. | Gabe Black | |
| 2009-07-27 | ARM: Implement a basic version of the fmxr instruction. | Gabe Black | |
| 2009-07-27 | ARM: Implement a basic version of the fmrx instruction. | Gabe Black | |
| 2009-07-27 | ARM: Add in spots for the VFP control registers. | Gabe Black | |
| 2009-07-27 | ARM: Fix the CLZ instruction. | Gabe Black | |
| 2009-07-27 | ARM: Initialize the CPSR so that we're in user mode. | Gabe Black | |
| 2009-07-27 | ARM: Set up the initial stack frame to match a recent Linux. | Gabe Black | |
| 2009-07-27 | Elf: Add in some new aux vector type constants. | Gabe Black | |
| 2009-07-27 | ARM: Make native trace only print when registers are changing value. | Gabe Black | |
| When registers have incorrect values but aren't actively changing, it's likely they're not being modified at all. The fact that they're still wrong isn't very important. | |||
| 2009-07-27 | ARM: Add a native tracer. | Gabe Black | |
| --HG-- rename : src/arch/sparc/SparcNativeTrace.py => src/arch/arm/ArmNativeTrace.py rename : src/arch/sparc/nativetrace.cc => src/arch/arm/nativetrace.cc rename : src/arch/sparc/nativetrace.hh => src/arch/arm/nativetrace.hh | |||
| 2009-07-27 | ARM: Fix fstat/fstat64 structs to match EABI definitions. | Ali Saidi | |
| 2009-07-27 | ARM: Handle register indexed system calls. | Ali Saidi | |
| 2009-07-27 | ARM: Detect OABI binaries and complain that they're no-longer supported. | Ali Saidi | |
| 2009-07-25 | SPARC: Fix a minor compile bug in native trace on gcc > 4.1. | Gabe Black | |
| 2009-07-25 | o3-smt: enforce numThreads parameter for SMT SE mode | Korey Sewell | |
| 2009-07-22 | Fixed the licences plus minor fixes for compilation | Polina Dudnik | |
| 2009-07-22 | MIPS: Small fix I forgot to qrefresh into my last change. | Gabe Black | |
| 2009-07-22 | MIPS: Style/formatting sweep of the decoder itself. | Gabe Black | |
| 2009-07-21 | MIPS: Format the register index constants like the other ISAs. | Gabe Black | |
| Also a few more style fixes. | |||
| 2009-07-21 | Automated merge with ssh://m5sim.org//repo/m5 | Derek Hower | |
| 2009-07-21 | ruby: fixed sequencer RMW data bug | Derek Hower | |
| 2009-07-21 | ruby: libruby_init now takes parsed Ruby-lang config text | Derek Hower | |
| libruby_init now expects to get a file that contains the output of running a ruby-lang configuration, opposed to the ruby-lang configuration itself. | |||
| 2009-07-21 | MIPS: Get MIPS_FS to compile, more style fixes. | Gabe Black | |
| Some breakage was from my BitUnion change, some was much older. | |||
| 2009-07-21 | MIPS: Many style fixes. | Gabe Black | |
| White space, commented out code, some other minor fixes. | |||
| 2009-07-20 | isa_parser: Get rid of the now unused ControlBitfieldOperand. | Gabe Black | |
| 2009-07-20 | MIPS: Use BitUnions instead of bits() functions and constants. | Gabe Black | |
| Also fix style issues in regions around these changes. | |||
| 2009-07-20 | merge | Derek Hower | |
| 2009-07-20 | ruby: moved cache stats from Profiler to CacheMemory | Derek Hower | |
| Caches are now responsible for their own statistic gathering. This requires a direct callback from the protocol on misses, and so all future protocols need to take this into account. | |||
| 2009-07-19 | CPU: Separate out native trace into ISA (in)dependent code and SimObjects. | Gabe Black | |
| --HG-- rename : src/cpu/nativetrace.cc => src/arch/sparc/nativetrace.cc rename : src/cpu/nativetrace.hh => src/arch/sparc/nativetrace.hh rename : src/cpu/NativeTrace.py => src/arch/x86/X86NativeTrace.py | |||
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index : gem5 | |
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