summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Expand)Author
2012-01-31clang: Enable compiling gem5 using clang 2.9 and 3.0Koan-Sin Tan
2012-01-31MEM: Remove the otherPort from the cache portsAndreas Hansson
2012-01-31Thread: Use inherited baseCpu rather than cpu in SimpleThreadAndreas Hansson
2012-01-31util: implements "writefile" gem5 op to export file from guest to host filesy...Dam Sunwoo
2012-01-31CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5Geoffrey Blake
2012-01-30MEM: Make the RubyPort physMemPort a PioPort instead of M5PortAndreas Hansson
2012-01-30MEM: Clean-up of Functional/Virtual/TranslatingPort remnantsAndreas Hansson
2012-01-28O3 CPU LSQ: Implement TSONilay Vaish
2012-01-27ns_gige: Fix a missing curly brace in if-statementAndreas Hansson
2012-01-12Fix memory corruption issue with CopyStringOut()Mitchell Hayenga
2012-01-25sim: display final value of curTick in statsAli Saidi
2012-01-25Mem: Add simple bandwidth stats to PhysicalMemoryAli Saidi
2012-01-23O3, Ruby: Forward invalidations from Ruby to O3 CPUNilay Vaish
2012-01-23MemCmd: Add a command for invalidation requests to LSQNilay Vaish
2012-01-17MEM: Make the bus default port yet another portAndreas Hansson
2012-01-17MEM: Removing the default port peer from Python portsAndreas Hansson
2012-01-17MEM: Make the bus bridge unidirectional and fixed address rangeAndreas Hansson
2012-01-17MEM: Remove the functional ports from the memory systemWilliam Wang
2012-01-17MEM: Separate queries for snooping and address rangesAndreas Hansson
2012-01-17MEM: Remove Port removeConn and MemObject deletePortRefsAndreas Hansson
2012-01-17MEM: Remove the notion of the default portAndreas Hansson
2012-01-17MEM: Simplify ports by removing EventManagerAndreas Hansson
2012-01-17CPU: Moving towards a more general port across CPU modelsAndreas Hansson
2012-01-17MEM: Add port proxies instead of non-structural portsAndreas Hansson
2012-01-17Ruby: Change the access permissions for MOESI hammerAndreas Hansson
2012-01-17MEM: Add the system port as a central access pointAndreas Hansson
2012-01-17MEM: Differentiate functional cache accesses from CPU and memoryAndreas Hansson
2012-01-16Alpha: warn_once about broken PAL breakpoints.Steve Reinhardt
2012-01-16debug: fix AllFlags::disable()Steve Reinhardt
2012-01-12inorder: MDU deadlock fixMaximilien Breughe
2012-01-12mips: compatibility between MIPS_SE and cross compiler from CodeSorceryDeyuan Guo
2012-01-12mips: Fix bugs in faults.cc/hh and tlb.cc for MIPS_FSDeyuan Guo
2012-01-12mips: Fix decoder of two float-convert instructionsDeyuan Guo
2012-01-12mips: definition of MIPS64_QNAN in registers.hhDeyuan Guo
2012-01-12PerfectCacheMemory: Remove references to CacheMsgNilay Vaish
2012-01-11Packet: Put back part of the assertAli Saidi
2012-01-11Packet: Remove meaningless assert statementAli Saidi
2012-01-11Ruby: Resurrect Cache Warmup CapabilityNilay Vaish
2012-01-11Ruby Debug Flags: Remove one, add anotherNilay Vaish
2012-01-11Ruby Port: Add a list of cpu ports attached to this portNilay Vaish
2012-01-11Ruby EventQueue: Remove unused functionsNilay Vaish
2012-01-11Ruby Sparse Memory: Add function for collating blocksNilay Vaish
2012-01-11Ruby: Add infrastructure for recording cache contentsNilay Vaish
2012-01-11Ruby Memory Vector: Functions for collating and populating pagesNilay Vaish
2012-01-10Ruby: remove the files related to the tracerNilay Vaish
2012-01-10MOESI Hammer: Remove a couple of bugsNilay Vaish
2012-01-10Sparse Memory: Simplify the structure for an entryNilay Vaish
2012-01-10Automated merge with ssh://repo.gem5.org/gem5Ali Saidi
2012-01-10config: Fix json output for Python lt 2.6.Ali Saidi
2012-01-10DPRINTF: Improve some dprintf messages.Nilay Vaish