Age | Commit message (Collapse) | Author |
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extra : convert_revision : b3e9fa094d68f608865dedfc9f3f4125a20fd748
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into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
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python does it all)
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src/cpu/simple/base.cc:
Make a microcoded op start at the current micropc, rather than starting at 0.
src/cpu/thread_state.cc:
Serialize the microPC and nextMicroPC
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extra : convert_revision : 5302215f17312ecef3ff4c6548acb05297ee4ff6
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in the future for micro insts.
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extra : convert_revision : ab6cd69f82b2013d66a91beaa3e39d8f417a9251
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src/arch/sparc/isa/decoder.isa:
Fix up the casa and casxa instructions.
src/arch/sparc/isa/formats/formats.isa:
This is handled in loadstore.isa now
src/arch/sparc/isa/formats/mem/basicmem.isa:
src/arch/sparc/isa/formats/mem/blockmem.isa:
Renamed doSplitExecute to doDualSplitExecute. This differentiates between the version that does both a register and immediate version, and one that just does a register version.
src/arch/sparc/isa/formats/mem/mem.isa:
The cas format is handled in loadstore.isa as well now.
src/arch/sparc/isa/formats/mem/util.isa:
Reorganized things a bit to better support cas
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extra : convert_revision : 12411e89e763287e52f9825bf7a417b263c1037f
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the integer microcode register.
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extra : convert_revision : 7df5bd4bbe8a2607c7d2b4799826831d6a440926
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extra : convert_revision : f23dbfdfe44e8e6cdd6948000669ad4f743b9fb4
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into zeep.pool:/z/saidi/work/m5.newmem.head
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extra : convert_revision : df73fd850d6638cbce6ff31203857f51235b8763
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extra : convert_revision : 4762b8ab46ac755726cc658a378c2cf5b2061dc3
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem
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extra : convert_revision : bedf422d51a52b009390b1e94f5330f752be2b87
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into zeep.pool:/z/saidi/work/m5.newmem.head
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extra : convert_revision : 473901bcd44bd2c563a3293d7326cd5aed8b630f
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into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
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extra : convert_revision : 30a912cf5d3f205a6301d291dd1799da21663056
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scan all packets on a functional access.
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extra : convert_revision : c735a6408443b5cc90d1c1841c7aeb61e02ec6ae
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src/arch/sparc/isa/formats/priv.isa:
Fix the priv format so that it uses isa_parser operands rather than accessing the registers directly in checkCode. Also, the expressions needed to be negated.
src/arch/sparc/isa/operands.isa:
Added an Hpstate operand, and adjusted the numbering.
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extra : convert_revision : 4a70862df061aa9e1b9eab125c4c2fc839ac3b5a
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instructions so that the cwp is modified at the correct time (when handling the fault), and fixed the "done" instruction.
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src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
Added a function to do normal SPARC trap processing, and implemented the spill and fill faults for SE
src/arch/sparc/process.cc:
src/arch/sparc/process.hh:
Added fill and spill handlers which are stuffed into the processes address space. The location of these handlers are stored in fillStart and spillStart.
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extra : convert_revision : 59adb96570cce86f373fbc2c3e4c05abe1742d3b
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src/mem/packet.cc:
Copy size is calculated by END-BEGIN not BEGIN-END
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extra : convert_revision : bed03e63dc80bf24f21bad08e6553d7aab92c7b3
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into zeep.pool:/z/saidi/work/m5.newmem.head
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into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head
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extra : convert_revision : a077304e608753f50f4a12216901d156469eebe4
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into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
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extra : convert_revision : bb58679e101570d50c040519fb08ffbabfee7416
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this will cause an assertion when you do the CPU switch. instead, push the responsibility of the resume upwards towards the user - documented in se.py and fs.py so it should be ok.
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extra : convert_revision : 7530cf140844e18cc26df80057f8760f29ec952b
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extra : convert_revision : 3c165af27ea0e6c7f2a17819c1717d8900f54cc1
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into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
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extra : convert_revision : 161c35ade82f2471e605d948dca56cfa216693fd
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change warning to a DPRINTF.
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extra : convert_revision : 819bade049d7ffd97d316051c99146ece5e3a651
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src/cpu/base_dyn_inst.hh:
Extend BaseDynInst a little bit so it can be use as a TC as well (specifically for ll/sc code).
src/cpu/base_dyn_inst_impl.hh:
Add variable to track if the result of the instruction should be recorded.
src/cpu/o3/alpha/cpu_impl.hh:
Clear lock flag upon hwrei.
src/cpu/o3/lsq_unit.hh:
Use ISA specified handling of locked reads.
src/cpu/o3/lsq_unit_impl.hh:
Use ISA specified handling of locked writes.
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extra : convert_revision : 1f5c789c35deb4b016573c02af4aab60d726c0e5
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extra : convert_revision : 6f181b15f37114ca0a3965cabcb2036bd2f97916
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with the timing cpu
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extra : convert_revision : 37358504c4d05d78d08c19ba3d0c99d38c4babf5
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem
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extra : convert_revision : cb15101d24ef2969e1819d6bdeeb2dd1f23f02d1
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