gem5 - gem5

Age	Commit message (Expand)	Author
2013-11-01	mem: Unify request selection for read and write queues	Neha Agarwal
2013-11-01	mem: Add a simple adaptive version of the open-page policy	Andreas Hansson
2013-11-01	mem: Just-in-time write scheduling in DRAM controller	Neha Agarwal
2013-11-01	mem: Add tRRD as a timing parameter for the DRAM controller	Andreas Hansson
2013-11-01	mem: Less conservative tRAS in DRAM configurations	Andreas Hansson
2013-11-01	mem: Make tXAW enforcement less conservative and per rank	Ani Udipi
2013-11-01	mem: Fix for 100% write threshold in DRAM controller	Neha Agarwal
2013-11-01	mem: Pick the next DRAM request based on bank availability	Andreas Hansson
2013-11-01	mem: Use the same timing calculation for DRAM read and write	Ani Udipi
2013-11-01	mem: Fix DRAM bank occupancy for streaming access	Ani Udipi
2013-11-01	mem: Schedule time for DRAM event taking tRAS into account	Ani Udipi
2013-11-01	mem: Add tRAS parameter to the DRAM controller model	Ani Udipi
2013-11-01	sim: Clarify the difference between tracing and debugging	Andreas Hansson
2013-10-31	ARM: add support for TEEHBR access	Chander Sudanthi
2013-10-31	dev: Add 'OSC' oscillator sys control reg support to VersatileExpress	Matt Evans
2013-10-31	dev: Add support for MSI-X and Capability Lists for ARM and PCI devices	Geoffrey Blake
2013-10-31	dev: Fix race conditions in IDE device on newer kernels	Geoffrey Blake
2013-10-31	base: Add support for ipv6 into inet.hh/inet.cc	Geoffrey Blake
2013-10-31	cpu: Construct ROB with cpu params struct instead of each variable	Faissal Sleiman
2013-10-31	config: Fix handling of parents for simobject vectors	Geoffrey Blake
2013-10-31	sim: added option to serialize SimLoopExitEvent	Dam Sunwoo
2013-10-31	mem: Add "const" attribute to Packet getters	Stephan Diestelhorst
2013-10-31	mem: Add privilege info to request class	Prakash Ramrakhyani
2013-10-31	cpu: Fix O3 issuse with load+barrier instructions.	Ali Saidi
2013-10-30	ruby: set SenderMachine in messages of MOESI_CMP_directory	Lluc Alvarez
2013-10-30	ruby: Fixed a deadlock when restoring a checkpoint with garnet	Emilio Castillo
2013-10-17	mem: De-virtualise interfaces in the CoherentBus	Stephan Diestelhorst
2013-10-17	cpu: add consistent guarding to *_impl.hh files.	Matt Horsnell
2013-10-17	mem: Add PortID to QueuedMasterPort constructor	Sascha Bischoff
2013-10-17	arm: Add a 'clear PPI' method to gic_pl390	Matt Evans
2013-10-17	config: Fix ommission of number base in ethernet address param	Geoffrey Blake
2013-10-17	config: Fix for port references generated multiple times	Geoffrey Blake
2013-10-17	dev: Add option to disable framebuffer .bmp dump in run folder	Dam Sunwoo
2013-10-17	cpu: Removing an unused variable in rename	Faissal Sleiman
2013-10-17	cpu: Change IEW DPRINTF to use IEW debug flag	Faissal Sleiman
2013-10-17	cpu: Put in assertions to check for maximum supported LQ/SQ size	Faissal Sleiman
2013-10-17	arm: Accomodate function name changes in newer linux kernels	Eric Van Hensbergen
2013-10-17	arm: Fix a GIC mask register bug	Ali Saidi
2013-10-17	cpu: Fix O3 uncacheable load that is replayed but misses the TLB	Ali Saidi
2013-10-17	mem: Make MemoryAccess flag more verbose	Ali Saidi
2013-10-17	build: Place proto output in the same directory, also for EXTRAS	Andreas Hansson
2013-10-17	dev: Allow additional UART interrupts to be set	Ali Saidi
2013-10-16	kvm: Fix latency calculation of IPR accesses	Andreas Sandberg
2013-10-15	ruby: eliminate non-determinism from ruby.stats output	Steve Reinhardt
2013-10-15	arch/x86: add support for explicit CC register file	Yasuko Eckert
2013-10-15	cpu: add a condition-code register class	Yasuko Eckert
2013-10-15	cpu/o3: clean up rename map and free list	Steve Reinhardt
2013-10-15	cpu: rename _DepTag constants to _Reg_Base	Steve Reinhardt
2013-10-15	isa: clean up register constants	Steve Reinhardt
2013-10-15	cpu/o3: clean up scoreboard object	Steve Reinhardt