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AgeCommit message (Expand)Author
2008-05-20SCons: Fixing SCons bug 2006 issues for non-alpha ISAsStephen Hines
2008-05-15Make sure that output files are always checked success before they're used.Ali Saidi
2008-05-06SCons: More scons fixing for SCons bug 2006Ali Saidi
2008-04-10SCons: add comments to SConscript documenting bug workaroundAli Saidi
2008-04-10PhysicalMemory: Add parameter for variance in memory delay.Ali Saidi
2008-04-08SCons: Manually specifying header only directories with Dir() works around th...Ali Saidi
2008-03-25IGbE: Fix bug that limits wire performance a bitAli Saidi
2008-03-25Automated merge with ssh://daystrom.m5sim.org//repo/m5Steve Reinhardt
2008-03-25Fix handling of writeback-induced writebacks in atomic mode.Steve Reinhardt
2008-03-25X86: Put an RTC into the CMOS part of the southbridge.Gabe Black
2008-03-25Devices: Separate out the MC146818 RTC so both Alpha and X86 can use it.Gabe Black
2008-03-25X86: Turn #defines into consts.Gabe Black
2008-03-25X86: Start implementing the south bridge stuff.Gabe Black
2008-03-25X86: Change the Opteron platform to be the PC platform.Gabe Black
2008-03-24Delete the Request for a no-response PacketSteve Reinhardt
2008-03-24Don't FastAlloc MSHRs since we don't allocate them on the fly.Steve Reinhardt
2008-03-24Add FAST_ALLOC_DEBUG and FAST_ALLOC_STATS as SConstruct options.Steve Reinhardt
2008-03-22Fix cache problem with writes to tempBlockSteve Reinhardt
2008-03-20MIPS: Check endianness of binaries in SE mode.Gabe Black
2008-03-17Fix a few Packet memory leaks.Steve Reinhardt
2008-03-17Restructure bus timing calcs to cope with pkt being deleted by target.Steve Reinhardt
2008-03-15Fix subtle cache bug where read could return stale dataSteve Reinhardt
2008-03-06MergeGabe Black
2008-03-06X86: Refine the local APIC.Gabe Black
2008-03-06O3CPU: Don't call dumpInsts if DEBUG is not definedVilas Sridharan
2008-03-01X86: Don't map the local APIC into the physical address space in SE mode.Gabe Black
2008-02-27Automated merge with ssh://daystrom.m5sim.org//repo/m5Steve Reinhardt
2008-02-27Add comments in code to describe bug conditions.Korey Sewell
2008-02-27Fix Load/Store Queue squashing after a SMT thread is removed but ensuringKorey Sewell
2008-02-27Fix offset in removeThread() function so that float registers start freeing upKorey Sewell
2008-02-26Revamp cache timing access mshr check to make stats sane again.Steve Reinhardt
2008-02-27Configs: Make using Simpoints easier with some config files that support them...Rick Strong
2008-02-26X86: Put in initial implementation of the local APIC.Gabe Black
2008-02-26X86: Implement the INVLPG instruction and the TIA microop.Gabe Black
2008-02-26TLB: Make a TLB base class and put a virtual demapPage function in it.Gabe Black
2008-02-26X86: Get PCI config space to work, and adjust address space prefix numbering ...Gabe Black
2008-02-26Cache: better comments particularly regarding writeback situation.Steve Reinhardt
2008-02-26Bus: Fix the bus timing to be more realistic.Gabe Black
2008-02-16Make L2+ caches allocate new block for writeback missesSteve Reinhardt
2008-02-14CPU: move the PC Events code to a place where the code won't be executed mult...Ali Saidi
2008-02-11Update copyright datesAli Saidi
2008-02-11Automated merge with file:/home/stever/hg/m5-origSteve Reinhardt
2008-02-11EXTRAS now points to src instead of needing 'src' subdir.Steve Reinhardt
2008-02-10Bus: Only update port cache when there is an item to update it with.Nicolas Zea
2008-02-10IGbE: Fix a couple of bugs.Ali Saidi
2008-02-10Fix #include lines for renamed cache files.Steve Reinhardt
2008-02-10Rename cache files for brevity and consistency with rest of tree.Steve Reinhardt
2008-02-06Make the Event::description() a const functionStephen Hines
2008-02-05Add base ARM code to M5Stephen Hines
2008-02-05Cleaned up os.path imports a bit.Steve Reinhardt
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