Age | Commit message (Collapse) | Author | |
---|---|---|---|
2008-06-28 | Backed out changeset 94a7bb476fca: caused memory leak. | Steve Reinhardt | |
2008-06-21 | Generate more useful error messages for unconnected ports. | Steve Reinhardt | |
Force all non-default ports to provide a name and an owner in the constructor. | |||
2008-06-18 | imported patch sim_object_params.diff | Nathan Binkert | |
2008-06-18 | AtomicSimpleCPU: Separate data stalls from instruction stalls. | Nathan Binkert | |
Separate simulation of icache stalls and dat stalls. | |||
2008-06-17 | Ethernet: share statistics between all ethernet devices and apply some | Nathan Binkert | |
of those statistics to the e1000 model. | |||
2008-06-17 | inet: initialization fixes. | Nathan Binkert | |
Make sure variables are properly initialized and also make sure that truth testing works properly. | |||
2008-06-17 | PacketFifo: Get slack out of the EthPacketData structure. This allows | Nathan Binkert | |
a packet to exist in multiple FIFOs if desired. | |||
2008-06-17 | ThreadState: Ensure that kernelStats is properly initialized | Nathan Binkert | |
2008-06-17 | rename MipsConsole to MipsBackdoor | Nathan Binkert | |
--HG-- rename : src/dev/mips/MipsConsole.py => src/dev/mips/MipsBackdoor.py rename : src/dev/mips/console.cc => src/dev/mips/backdoor.cc rename : src/dev/mips/console.hh => src/dev/mips/backdoor.hh | |||
2008-06-17 | rename AlphaConsole to AlphaBackdoor | Nathan Binkert | |
--HG-- rename : src/dev/alpha/AlphaConsole.py => src/dev/alpha/AlphaBackdoor.py rename : src/dev/alpha/console.cc => src/dev/alpha/backdoor.cc rename : src/dev/alpha/console.hh => src/dev/alpha/backdoor.hh | |||
2008-06-17 | Change the default output filename for the terminal so it's more obvious. | Nathan Binkert | |
--HG-- rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal | |||
2008-06-17 | Rename SimConsole to Terminal since it makes more sense | Nathan Binkert | |
--HG-- rename : src/dev/SimConsole.py => src/dev/Terminal.py rename : src/dev/simconsole.cc => src/dev/terminal.cc rename : src/dev/simconsole.hh => src/dev/terminal.hh | |||
2008-06-15 | physmem: Add a null option to physical memory so it doesn't store data. | Nathan Binkert | |
2008-06-15 | port: Clean up default port setup and port switchover code. | Nathan Binkert | |
2008-06-15 | params: Prevent people from setting attributes on vector params. | Nathan Binkert | |
2008-06-15 | add compile flags to m5 | Nathan Binkert | |
2008-06-14 | Command line option to print out List of SimObjects and their parameters | Nathan Binkert | |
2008-06-14 | main: add .m5/options.py processing. This file is processed before | Nathan Binkert | |
arguments are parsed so that they can change the default options for various config parameters. | |||
2008-06-14 | Add .m5 configuration directory | Nathan Binkert | |
2008-06-14 | python: Separate the options parsing stuff. Remove options parsing stuff from | Nathan Binkert | |
main.py so things are a bit more obvious. | |||
2008-06-14 | params: Fix the memory bandwidth parameter | Nathan Binkert | |
2008-06-14 | params: Fix floating point parameters | Nathan Binkert | |
2008-06-14 | python: Move various utility classes into a new m5.util package so | Nathan Binkert | |
they're all in the same place. This also involves having just one jobfile.py and moving it into the utils directory to avoid duplication. Lots of improvements to the utility as well. --HG-- rename : src/python/m5/attrdict.py => src/python/m5/util/attrdict.py rename : util/pbs/jobfile.py => src/python/m5/util/jobfile.py rename : src/python/m5/util.py => src/python/m5/util/misc.py rename : src/python/m5/multidict.py => src/python/m5/util/multidict.py rename : util/stats/orderdict.py => src/python/m5/util/orderdict.py | |||
2008-06-14 | MemReq: Add option to reset the time on a request. | Nathan Binkert | |
2008-06-14 | Fix various SWIG warnings | Nathan Binkert | |
2008-06-14 | Add missing dependencies on .i files | Nathan Binkert | |
2008-06-14 | scons: proper fix for hg version stuff | Nathan Binkert | |
2008-06-13 | scons: fix program_info.cc generation | Nathan Binkert | |
2008-06-13 | Automated merge with ssh://m5sim.org//repo/m5 | Steve Reinhardt | |
2008-06-13 | Get rid of bogus bus assertion. | Steve Reinhardt | |
It runs out that if a MemObject turns around and does a send in its receive callback, and there are other sends already scheduled, then it could observe a state where it's not at the head of the list but the bus's sendEvent is not scheduled (because we're still in the middle of processing the prior sendEvent). | |||
2008-06-13 | Get rid of bogus cache assertion. | Steve Reinhardt | |
I was asserting that the only reason you would defer targets is if a write came in while you had an outstanding read miss, but there's another case where you could get a read access after you've snooped an invalidation and buffered it because it applies to a prior outstanding miss. | |||
2008-06-13 | HG: Add compiled hg revision and date to the standard M5 output. | Ali Saidi | |
2008-06-12 | Alpha: Get rid of an old include of a non-existant file. | Gabe Black | |
2008-06-12 | Params: Allow nested namespaces in cxx_namespace | Gabe Black | |
2008-06-12 | X86: Make the cpuid processor identifier return a real string. | Gabe Black | |
2008-06-12 | X86: Make the code compile as 32 bit. | Gabe Black | |
2008-06-12 | Params: Remove an unnecessary include. | Gabe Black | |
2008-06-12 | X86: Make the e820 table manually or automatically configurable from python. | Gabe Black | |
2008-06-12 | X86: Make the disassembly for halt conform with the other microops. | Gabe Black | |
2008-06-12 | X86: Implement and hook up STI and CLI instructions. | Gabe Black | |
2008-06-12 | X86: Make sure there's something to catch when the kernel messes with ports ↵ | Gabe Black | |
"behind" the pci config magic ports. | |||
2008-06-12 | X86: Make the platform object initialize channel 0 of the PIT. | Gabe Black | |
2008-06-12 | X86: Hook the speaker device to the pit device. | Gabe Black | |
2008-06-12 | Timer: Fill out the periodic modes a little. | Gabe Black | |
2008-06-12 | Dev: Seperate the 8254 timer from tsunami and use it in that and the PC. | Gabe Black | |
2008-06-12 | BitUnion: Take out namespace declaration so bitunions can be declared inside ↵ | Gabe Black | |
classes. | |||
2008-06-12 | X86: Add an event for the apic timer timeout. It doesn't get used yet. | Gabe Black | |
2008-06-12 | X86: Rename the divide count register to divide configuration. | Gabe Black | |
2008-06-12 | X86: Make the apic isr and irr work. | Gabe Black | |
2008-06-12 | X86: Make the apic task priority register work. | Gabe Black | |