summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Expand)Author
2014-12-02scons: Ensure dictionary iteration is sorted by keyAndreas Hansson
2014-12-02mem: Support WriteInvalidate (again)Curtis Dunham
2014-12-02mem: Remove WriteInvalidate supportCurtis Dunham
2014-12-02cpu: Fix retries on barrier/store in Minor's store bufferAndrew Bardsley
2014-12-02cpu: Fix memoryIssueLimit checking in MinorAndrew Bardsley
2014-12-02arm: Fix TLB ignoring faults when table walkingAndrew Bardsley
2014-12-02cpu, o3: Ignored invalidate causing same-address load reorderingMarco Elver
2014-12-02cpu: Always mask the snoop address when performing lock checkAndreas Hansson
2014-12-02cpu: Move packet deallocation to recvTimingResp in the O3 CPUStephan Diestelhorst
2014-12-02mem: Relax packet src/dest check and shift onus to crossbarAndreas Hansson
2014-12-02mem: Clean up packet data allocationAndreas Hansson
2014-12-02mem: Cleanup Packet::checkFunctional and hasData usageAndreas Hansson
2014-12-02mem: Make the requests carried by packets constAndreas Hansson
2014-12-02mem: Make Request getters constAndreas Hansson
2014-12-02mem: Add checks and explanation for assertMemInhibit usageAndreas Hansson
2014-12-02mem: Assume all dynamic packet data is array allocatedAndreas Hansson
2014-12-02mem: Remove redundant Packet::allocate callsAndreas Hansson
2014-12-02mem: Use const pointers for port proxy write functionsAndreas Hansson
2014-12-02mem: Add const getters for write packet dataAndreas Hansson
2014-12-02mem: Remove null-check bypassing in Packet::getPtrAndreas Hansson
2014-12-02mem: Add a GDDR5 DRAM configOmar Naji
2014-11-24misc: Another round of static analysis fixupsAndreas Hansson
2014-11-23mem: Page Table map api modificationAlexandru Dutu
2014-11-23mem: Multi Level Page Table bug fixAlexandru Dutu
2014-11-23mem: Page Table long linesAlexandru Dutu
2014-11-23x86: Segment initialization to support KvmCPU in SEAlexandru Dutu
2014-11-23kvm, x86: Adding support for SE mode executionAlexandru Dutu
2014-11-23cpuid, x86: Enabling more features in CPUidAlexandru Dutu
2014-11-21x86: pc: Put a stub IO device at port 0xed which the kernel can use for delays.Gabe Black
2014-11-18dev: Use fixed size member variables to describe fixed size PL111 registers.Gabe Black
2014-11-17vnc: Add a conversion function for bgr888.Gabe Black
2014-11-17x86: Fix setting segment bases in real mode.Gabe Black
2014-11-17x86: Fix some bugs in the real mode far jmp instruction.Gabe Black
2014-11-17x86: APIC: Only set deliveryStatus if our IPI is going somewhere.Gabe Black
2014-11-17x86: APIC: Fix the getRegArrayBit function.Gabe Black
2014-11-16x86: Fix the CPUID Long Mode Address Size function.Gabe Black
2014-11-14arm: Fixes based on UBSan and static analysisAndreas Hansson
2014-11-14mem: Clarify unit of DRAM controller buffer sizeAndreas Hansson
2014-11-12mem: Delete unused variable in Garnet NetworkLinkMitch Hayenga
2014-11-12arm: Fix timing wakeup with LLSCAli Saidi
2014-11-12sim: Sort SimObject descendants and portsAndreas Hansson
2014-11-12base: Revert 9277177eccff and use getenv/setenv for UTC timeAndreas Hansson
2014-11-06x86 isa: This patch attempts an implementation at mwait.Marc Orr
2014-11-06cpu: Minor Draining BugAndrew Lukefahr
2014-11-06ruby: provide a backing storeNilay Vaish
2014-11-06ruby: interface with classic memory controllerNilay Vaish
2014-11-06ruby: remove the function functionalReadBuffers()Nilay Vaish
2014-11-06ruby: coherence protocols: remove data block from dirctory entryNilay Vaish
2014-11-06ruby: slicc: allow adding a bool to an int, like C++.Nilay Vaish
2014-11-06ruby: remove sparse memory.Nilay Vaish
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 21:17:13 +0000