gem5 - gem5

Age	Commit message (Expand)	Author
2012-01-11	Ruby Port: Add a list of cpu ports attached to this port	Nilay Vaish
2012-01-11	Ruby EventQueue: Remove unused functions	Nilay Vaish
2012-01-11	Ruby Sparse Memory: Add function for collating blocks	Nilay Vaish
2012-01-11	Ruby: Add infrastructure for recording cache contents	Nilay Vaish
2012-01-11	Ruby Memory Vector: Functions for collating and populating pages	Nilay Vaish
2012-01-10	Ruby: remove the files related to the tracer	Nilay Vaish
2012-01-10	MOESI Hammer: Remove a couple of bugs	Nilay Vaish
2012-01-10	Sparse Memory: Simplify the structure for an entry	Nilay Vaish
2012-01-10	Automated merge with ssh://repo.gem5.org/gem5	Ali Saidi
2012-01-10	config: Fix json output for Python lt 2.6.	Ali Saidi
2012-01-10	DPRINTF: Improve some dprintf messages.	Nilay Vaish
2012-01-09	X86: Add memory fence to I/O instructions	Nilay Vaish
2012-01-09	CPU: Remove Alpha-specific PC alignment check.	Anders Handler
2012-01-09	Config: Fix issue with JSON output	Ali Saidi
2012-01-09	Packet: Add derived class FunctionalPacket to enable partial functional reads	Geoffrey Blake
2012-01-09	stats: fix Vector2d to display stats correctly when y_subname is not specified.	Dam Sunwoo
2012-01-09	sim: Enable sampling of run-time for code-sections marked using pseudo insts.	Prakash Ramrakhyani
2012-01-09	O3: Remove some asserts that no longer seem to be valid.	Ali Saidi
2012-01-09	config: support outputing a pickle of the configuration tree	Ali Saidi
2012-01-09	mem: Change DPRINTF prints more useful destination port number.	Min Kyu Jeong
2012-01-09	O3: Add support of function tracing with O3 CPU.	Ali Saidi
2012-01-09	ARM: Add support for running multiple systems	Ali Saidi
2012-01-09	ARM: Add support for initparam m5 op	Ali Saidi
2012-01-09	Base: Fixed shift amount in genrand() to work with large numbers	Dam Sunwoo
2012-01-09	SWIG: Make gem5 compile and link with swig 2.0.4	Andreas Hansson
2012-01-09	MAC: Make gem5 compile and run on MacOSX 10.7.2	Andreas Hansson
2012-01-07	Ruby Cache: Add param for marking caches as instruction only	Nilay Vaish
2012-01-07	Another merge with the main repository.	Gabe Black
2012-01-07	Merge with the main repository again.	Gabe Black
2012-01-07	Merge with main repository.	Gabe Black
2012-01-06	AbstractController: Remove some of the unused functions	Nilay Vaish
2012-01-06	Ruby Set: Move NUMBER_WORDS_PER_SET to Set.hh	Nilay Vaish
2012-01-05	eventq: add a function for replacing head of the queue	Nilay Vaish
2012-01-05	MESI Coherence Protocol: Fix L2 miss statistics	Nilay Vaish
2012-01-05	X86 TLB: Move a DPRINTF to its correct place	Nilay Vaish
2011-12-31	Ruby: Shuffle some of the included files	Nilay Vaish
2011-12-31	SLICC: Use pointers for directory entries	Nilay Vaish
2011-12-15	IO: Fix bug in DMA Device where receiving a snoop on DMA port would cause a p...	Ali Saidi
2011-12-13	gcc: fix unused variable warnings from GCC 4.6.1	Nathan Binkert
2011-12-01	Trace: FIx issue with creation of trace file with output dir overhaul.	Ali Saidi
2011-12-01	MOESI_hammer: fixed L2 to L1 infinite stalls and deadlock	Brad Beckmann
2011-12-01	physmem: Improved fatal message for size mismatch	Brad Beckmann
2011-12-01	VNC: Add support for capturing frame buffer to file each time it is changed.	Chris Emmons
2011-12-01	Output: Add hierarchical output support and cleanup existing codebase.	Chris Emmons
2011-12-01	SE: Don't warn when not extending stack as it's too noisy with O3.	Ali Saidi
2011-12-01	O3: Remove hardcoded tgts_per_mshr in O3CPU.py.	Chander Sudanthi
2011-12-01	Device: Make changes necessary to support a coherent page walker cache.	Mitchell Hayenga
2011-12-01	ARM: Add support for having a TLB cache.	Ali Saidi
2011-12-01	ARM: Add IsSerializeAfter and IsNonSpeculative flag to the syscall instruction .	Ali Saidi
2011-12-01	O3: Add stat that counts how many cycles the O3 cpu was quiesced.	Ali Saidi