Age | Commit message (Collapse) | Author |
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removed from the other ones as well.
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extra : convert_revision : 0c07534de42d6c32ac26d9e43709111e3ab30d57
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little better.
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extra : convert_revision : 3a1b7856e6143ca089fd6e36492608377dfede19
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-sparc32
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extra : convert_revision : a7697ea8457a03318e3fcf34775bf3ecc4786e8a
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into pb15.local:/Users/ali/work/m5.newmem
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extra : convert_revision : 887b278dac6db5ea17ade641de84d0ab8b05db96
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-sparc32
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extra : convert_revision : 70dcd9d1d669c1c619411389487b7910861550e3
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undefined opcodes in impdep2 (which in SE is all of them) trap with an illegal_instruction exception.
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extra : convert_revision : dd7848d0685e4cc6f5fd5e3b846a3f70b62ee30a
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extra : convert_revision : d88784736df5f9b498770fb7e98f52715669c0e1
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into pb15.local:/Users/ali/work/m5.newmem
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extra : convert_revision : e0057583132ce545eb1867b446484e8984b97282
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relevant code directly into the SimConsole object. Now,
you can easily turn off the listen port by just specifying
0 as the port.
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extra : convert_revision : c8937fa45b429d8a0728e6c720a599e38972aaf0
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extra : convert_revision : ce7ac94da0ed6bad457a8a9e4c949b0c3b09c2ae
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initialized.
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extra : convert_revision : b4b156ed8e3c0c4c4f8043ff86dc232ebad38668
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extra : convert_revision : 4970a76890a3256073423a827dd0c55cfcb19a08
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : 4105ebbeca59206bece27f229ee810d594fb4310
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util/m5/Makefile.alpha:
Clean up to make it a bit easier to muck with
util/m5/Makefile.alpha:
Make the makefile more reasonable
util/m5/Makefile.alpha:
Remove authors from copyright.
util/m5/Makefile.alpha:
Updated Authors from bk prs info
util/m5/Makefile.alpha:
bk cp Makefile Makefile.alpha
src/arch/sparc/tlb.cc:
Clean up the cache code a little bit and make sure the uncacbale bit is set when appropriate
src/arch/alpha/isa/decoder.isa:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
Rename AlphaPseudo -> PseudoInst since it's all generic
src/arch/sparc/isa/bitfields.isa:
src/arch/sparc/isa/decoder.isa:
src/arch/sparc/isa/includes.isa:
src/arch/sparc/isa/operands.isa:
Add support for pseudo instructions in sparc
util/m5/Makefile.alpha:
util/m5/Makefile.sparc:
split off alpha make file and sparc make file for m5 app
util/m5/m5.c:
ivle and ivlb aren't used anymore
util/m5/m5op.h:
stdint seems like a more generic better fit here
util/m5/m5op_alpha.S:
move the op ids into their own header file since we can share them between sparc and alpha
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rename : util/m5/Makefile => util/m5/Makefile.sparc
rename : util/m5/m5op.S => util/m5/m5op_alpha.S
extra : convert_revision : 490ba2e8b8bc6e28bfc009cedec6b686b28e7834
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This basically involves moving the builder code outside of any
namespace. While we're at it, move a few braces outside of
a couple #if/#else/#endif blocks so it's easier to match up
the braces.
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extra : convert_revision : a7834532aadc63b0e0ff988dd5745049e02e6312
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specified.
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extra : convert_revision : 49c1ea0b8c313949124aed84b1055db0b3c55bd8
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based on the swig modules that we have
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extra : convert_revision : 2fd12db39d46608a62b9df36c2b36189f1d2bc30
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this is just a shuffling around of code and fixes to make
stuff commit properly
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extra : convert_revision : a057f7fe4962cfc6200781ff66d2c26bf9c6eb8c
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extra : convert_revision : fda9ab0d04f77f27810018a8639d6ea8abb59326
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : 10d4dc08411c7a433a7194e94f69ca1d639a1ce7
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src/arch/alpha/vtophys.cc:
src/arch/alpha/vtophys.hh:
src/arch/sparc/arguments.hh:
move Copy* to vport since it's generic for all the ISAs
src/arch/sparc/isa_traits.hh:
the Solaris kernel sets up a virtual-> real mapping for all memory starting at SegKPMBase
src/arch/sparc/pagetable.hh:
add a class for getting bits out of the TteTag
src/arch/sparc/remote_gdb.cc:
add 32bit support kinda.... If its 32 bit
src/arch/sparc/remote_gdb.hh:
Add 32bit register offsets too.
src/arch/sparc/tlb.cc:
cleanup generation of tsb pointers
src/arch/sparc/tlb.hh:
add function to return tsb pointers for an address
make lookup public so vtophys can use it
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
write vtophys for sparc
src/base/bitfield.hh:
return a mask of bits first->last
src/mem/vport.cc:
src/mem/vport.hh:
move Copy* here since it's ISA generic
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extra : convert_revision : c42c331e396c0d51a2789029d8e232fe66995d0f
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relevant stuff has now been moved to python.
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extra : convert_revision : 608e5ffd0e2b33949a2b183117216f136cfa4484
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since they're no longer used
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extra : convert_revision : e39590aa03cc4c961d2eb5dab57862811f431e4d
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expose all of the relevant functionality to python. Clean
up the mysql code while we're at it.
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extra : convert_revision : 5b711202a5a452b8875ebefb136a156b65c24279
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to loop through it. This is more important as we get rid
of param contexts
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extra : convert_revision : 5a24048b5c3d609285da83dfcb106910afad6919
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extra : convert_revision : ef5f3492e8232d08af7e1eae64ba96c79ca14b6f
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extra : convert_revision : 6357ade64deb42fae68b2766545b1c4cdc673fc9
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on in python. Fix the trace start code so it actually starts
when it is suppsed to. Make the Exec tracing stuff obey the
trace enabled flag.
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extra : convert_revision : 634ba0b4f52345d4bf40d43e239cef7ef43e7691
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back into python so we don't just silently ignore those errors
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extra : convert_revision : e2f5566a4681f1b8ea80af50071119118afa7d8a
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : f9fd4df544144a691bb5956e3f84036a61822547
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extra : convert_revision : 5edf0ad492fe438d66bcf0ae469ef841cd71e157
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into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem
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extra : convert_revision : 4878ca509f9982c065933a41ffc87808edb08b00
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extra : convert_revision : 6cd2dc622ca95cc1ea89bd5e5cbf33d9510c351c
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src/dev/alpha/tsunamireg.h:
get rid of things that aren't really tsunami registers
src/dev/platform.hh:
src/dev/uart.cc:
the uart pointer isn't used anymore
src/dev/simconsole.cc:
make the simconsole print something more useful to distinguish between various consoles in a single system
src/dev/uart8250.hh:
put the needed uart defines in here rather than including them from tsunamireg
src/python/m5/objects/T1000.py:
add a console to the T1000 config for the hypervisor
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extra : convert_revision : 76ca92122e611eaf76b989bc699582eef8297be8
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for store conditional.
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extra : convert_revision : 73efd2ca17994e0e19c08746441874a2ac8183af
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extra : convert_revision : 9ecfd5a0a151c03503e42faf98240da12fd719b1
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the traceflags infrastructure. InstExec is now just Exec
and all of the command line options are now trace options.
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extra : convert_revision : 4adfa9dfbb32622d30ef4e63c06c7d87da793c8f
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the script is invoked as main. This allows us to import traceflags.py
if we just want the list of available flags.
Embed traceflags.py into the zipfile so it can be accessed from the
python side of things. With this, print an error on invalid flags and
add --trace-help option that will print out the list of trace flags
that are compiled in. If a flag is prefixed with a '-', now that flag
will be disabled.
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extra : convert_revision : 2260a596b07d127c582ff73474dbbdb0583db524
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extra : convert_revision : 213440066c700ed5891a6d4568928b7f3f2fe750
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extra : convert_revision : 5bfe4b943ca5b3e30a7097a46cab4f93dadd714f
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into zeep.pool:/z/saidi/work/m5.newmem
src/cpu/simple/atomic.cc:
merge steve's changes in.
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extra : convert_revision : a17eda37cd63c9380af6fe68b0aef4b1e1974231
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conditional swaps as well
Add support for a twin 64 bit int load
Add Memory barrier and write barrier flags as appropriate
Make atomic memory ops atomic
src/arch/alpha/isa/mem.isa:
src/arch/alpha/locked_mem.hh:
src/cpu/base_dyn_inst.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_impl.hh:
rename store conditional stuff as extra data so it can be used for conditional swaps as well
src/arch/alpha/types.hh:
src/arch/mips/types.hh:
src/arch/sparc/types.hh:
add a largest read data type for statically allocating read buffers in atomic simple cpu
src/arch/isa_parser.py:
Add support for a twin 64 bit int load
src/arch/sparc/isa/decoder.isa:
Make atomic memory ops atomic
Add Memory barrier and write barrier flags as appropriate
src/arch/sparc/isa/formats/mem/basicmem.isa:
add post access code block and define a twinload format for twin loads
src/arch/sparc/isa/formats/mem/blockmem.isa:
remove old microcoded twin load coad
src/arch/sparc/isa/formats/mem/mem.isa:
swap.isa replaces the code in loadstore.isa
src/arch/sparc/isa/formats/mem/util.isa:
add a post access code block
src/arch/sparc/isa/includes.isa:
need bigint.hh for Twin64_t
src/arch/sparc/isa/operands.isa:
add a twin 64 int type
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
add support for twinloads
add support for swap and conditional swap instructions
rename store conditional stuff as extra data so it can be used for conditional swaps as well
src/mem/packet.cc:
src/mem/packet.hh:
Add support for atomic swap memory commands
src/mem/packet_access.hh:
Add endian conversion function for Twin64_t type
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
Add support for atomic swap memory commands
Rename sc code to extradata
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extra : convert_revision : 69d908512fb34a4e28b29a6e58b807fb1a6b1656
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into vm1.(none):/home/stever/bk/newmem-head
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extra : convert_revision : 496428e23050122a8a0029e5fddea261bef5729e
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function into Alpha ISA description. write now just generically
returns a result value if the res pointer is non-null (which means
we can only provide a res pointer if we expect a valid result
value).
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extra : convert_revision : fb1c315515787f5fbbf7d1af7e428bdbfe8148b8
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extra : convert_revision : 84114216854dfcd468115bbf5398333e98056a58
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its not all that useful. Fix a few bugs with python/C++
integration.
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extra : convert_revision : a706512f7dc8b0c88f1ff96fe35ab8fbf9548b78
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We don't currently use randomness much, so I didn't go too far, but
in the future, we may want to actually expose the random number values
themselves to python. For now, I'll at least let you seed it.
While we're at it, clean up a clearly bad way for generating random
doubles.
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extra : convert_revision : df2aa8b58dd0d9c2a7c771668a760b2df8db1e11
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--HG--
extra : convert_revision : b6a975d1c4195a764ba875bc3aaaa064be4955b7
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access to enabling/disabling tracing. Command line is
unchanged except for the removal of --trace-cycle since
it's not so clear what that means.
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extra : convert_revision : c0164d92d3615d76d0c6acaabaafd92a9278212a
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--HG--
extra : convert_revision : 4e9fda42e9f5ed3e9f66e5bd178c45537792073b
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