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2006-12-16Merge zizzer:/bk/newmemGabe Black
into zower.eecs.umich.edu:/eecshome/m5/newmem src/arch/isa_parser.py: src/arch/sparc/isa/formats/mem/basicmem.isa: src/arch/sparc/isa/formats/mem/blockmem.isa: src/arch/sparc/isa/formats/mem/util.isa: src/arch/sparc/miscregfile.cc: src/arch/sparc/miscregfile.hh: src/cpu/o3/iew_impl.hh: Hand Merge --HG-- extra : convert_revision : ae1b25cde85ab8ec275a09d554acd372887d4d47
2006-12-16Switch the endianness of data that's forwarded. This is the same sort of ↵Gabe Black
problem that was happening when stores went all the way to memory and back. --HG-- extra : convert_revision : 09fece7ae934f542e51046d33505df3f7ec0b919
2006-12-16Make fetch detect when a branch is happening, rather than trying to compute ↵Gabe Black
when. --HG-- extra : convert_revision : 1a8edc004570abb48e6c4cdf1b43c5699866838e
2006-12-16Accidently "cleaned" away the NPC parameter to the constructor.Gabe Black
--HG-- extra : convert_revision : 46670ee86000dfb171d327eb8f58555a4afb2360
2006-12-16Don't have "predict" set the predicted target of the instruction. Do that ↵Gabe Black
explicitly when you use predict. --HG-- extra : convert_revision : 8b613bb365b31ffaef1cea9fd789abe46219bdcf
2006-12-16Add in constants which let you explicitly check if endian conversion would ↵Gabe Black
do anything. This was needed for a case where a piece of data was within a larger data type. When the larger data type was swapped, the location of the smaller data type would move. --HG-- extra : convert_revision : 4c904c964678529c72b8f1044dfcb400604f6654
2006-12-16Add in capability to return to unblocking after a squash. This is needed ↵Gabe Black
because if you don't squash -all- the instructions, you need to keep clearing out whatever is left in the skid buffer. --HG-- extra : convert_revision : 7308eda27f4366348cf5fce71ddfa4b217bc172d
2006-12-16Make sure endian conversion is done on the memory data when it's just set to ↵Gabe Black
an existing buffer. --HG-- extra : convert_revision : 5a890091b6a31b5414acbf68f19e28d7122a98d7
2006-12-16Make the decoder use the new setup in the dyninsts for branch prediction.Gabe Black
--HG-- extra : convert_revision : 9a6d6c93e5b40a55774891df54d290ff557b322c
2006-12-16Made branch delay slots get squashed, and passed back an NPC and NNPC to ↵Gabe Black
start fetching from. --HG-- extra : convert_revision : a2e4845fedf113b5a2fd92d3d28ce5b006278103
2006-12-16Added a predicted NPC field, explicitly stored whether the instruction was ↵Gabe Black
predicted taken or not. --HG-- extra : convert_revision : ba668af302ca4d8a3a032e907d5058e1477f462a
2006-12-16Made changes to CWP be non speculative.Gabe Black
--HG-- extra : convert_revision : 43899bc97061c33e67a53179c23e46b079118117
2006-12-16Changes to the isa_parser and affected files to fix an indexing problem with ↵Gabe Black
split execute instructions and miscregs aliasing with integer registers. src/arch/isa_parser.py: Rearranged things so that classes with more than one execute function treat operands properly. 1. Eliminated the CodeBlock class 2. Created a SubOperandList 3. Redefined how InstObjParams is constructed To define an InstObjParam, you can either pass in a single code literal which will be named "code", or you can pass in a dictionary of code snippets which will be substituted into the Templates. In order to get this to work, there is a new restriction that each template has only one function in it. These changes should only affect memory instructions which have regular and split execute functions. Also changed the MiscRegs so that they use the instrunctions srcReg and destReg arrays. src/arch/sparc/isa/formats/basic.isa: src/arch/sparc/isa/formats/branch.isa: src/arch/sparc/isa/formats/integerop.isa: src/arch/sparc/isa/formats/mem/basicmem.isa: src/arch/sparc/isa/formats/mem/blockmem.isa: src/arch/sparc/isa/formats/mem/util.isa: src/arch/sparc/isa/formats/nop.isa: src/arch/sparc/isa/formats/priv.isa: src/arch/sparc/isa/formats/trap.isa: Rearranged to work with new InstObjParam scheme. src/cpu/o3/sparc/dyn_inst.hh: Added functions to access the miscregs using the indexes from instructions srcReg and destReg arrays. Also changed the names of the other accessors so that they have the suffix "Operand" if they use those arrays. src/cpu/simple/base.hh: Added functions to access the miscregs using the indexes from instructions srcReg and destReg arrays. --HG-- extra : convert_revision : c91e1073138b72bcf4113a721e0ed40ec600cf2e
2006-12-15Merge zizzer:/bk/newmemLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem --HG-- extra : convert_revision : a6a40a3bc2e07bc7828de08fa2ce1c847105483d
2006-12-15small change to eliminate address range overlap.Lisa Hsu
--HG-- extra : convert_revision : c8309a8774265a707c87c4f516bec1f81aff4a79
2006-12-15little fixes i noticed while searching for reason for address range issues ↵Lisa Hsu
(but these weren't the cause of the problem). RangeSize as a function takes a start address, and a SIZE, and will make the range (start, start+size-1) for you. src/cpu/memtest/memtest.hh: src/cpu/o3/fetch.hh: src/cpu/o3/lsq.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/simple/atomic.hh: src/cpu/simple/timing.hh: Fix RangeSize arguments src/dev/alpha/tsunami_cchip.cc: src/dev/alpha/tsunami_io.cc: src/dev/alpha/tsunami_pchip.cc: src/dev/baddev.cc: pioSize indicates SIZE, not a mask --HG-- extra : convert_revision : d385521fcfe58f8dffc8622260937e668a47a948
2006-12-15Merge zizzer:/bk/sparcfsLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5 --HG-- extra : convert_revision : 2f11b5f9fa6356cbf9f98c8cd7d4f6fbfaf9d24d
2006-12-15some small general fixes to make everythign work nicely with other ISAs, now ↵Lisa Hsu
we can merge back with newmem. exetrace.cc: wrap this variable between FULL_SYSTEM #ifs mmaped_ipr.hh: fix for build miscregfile.cc: fixes for HPSTATE access during SE mode src/arch/sparc/miscregfile.cc: fixes for HPSTATE access during SE mode src/arch/mips/mmaped_ipr.hh: fix for build src/cpu/exetrace.cc: wrap this variable between FULL_SYSTEM #ifs --HG-- extra : convert_revision : c5b9d56ab99018a91d04de47ba1d5ca7768590bb
2006-12-15tlb.cc:Lisa Hsu
fix namespace indentations src/arch/alpha/tlb.cc: fix namespace indentations --HG-- extra : convert_revision : 327d5a1568ba60cab1c1ae4bb3963ea78dfe0176
2006-12-15Use my range_map to speed up findPort() in the bus. The snoop code could ↵Ali Saidi
still use some work. --HG-- extra : convert_revision : ba0a68bd378d68e4ebd80a101b965d36c8be1db9
2006-12-15Optimized the TLB translations with some cachingAli Saidi
--HG-- extra : convert_revision : f79f863393f918ff9363b2c261f8c0dfec64312e
2006-12-14flesh out twinx asisAli Saidi
fix TICK register reads reduce the number of readmiscreg accesses, implement tsb pointer stuff src/arch/sparc/asi.cc: flesh out twinx asis src/arch/sparc/miscregfile.cc: fix TICK register reads src/arch/sparc/tlb.cc: reduce the number of readmiscreg accesses, implement tsb pointer stuff --HG-- extra : convert_revision : 1995c3b04b7743c6122cbf8ded7c4d5de48fa3c8
2006-12-13Split CachePort class into CpuSidePort and MemSidePortSteve Reinhardt
and push those into derived Cache template class to eliminate a few layers of virtual functions and conditionals ("if (isCpuSide) { ... }" etc.). --HG-- extra : convert_revision : cb1b88246c95b36aa0cf26d534127d3714ddb774
2006-12-13Merge zizzer:/bk/newmemLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5 --HG-- extra : convert_revision : 8cf3e824e4892249b12ed0fd92bb310748b18fa2
2006-12-13fix MiscRegFile::readRegWithEffect, which neglected the MISCREGS.Lisa Hsu
--HG-- extra : convert_revision : 4fdffe01b8e63e24b97a2e4194c747e6cf5e25ba
2006-12-13Merge zizzer:/bk/newmemLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5 --HG-- extra : convert_revision : 82733f9c7bf833cf6bbfbd2aad292f69f52d21bc
2006-12-13Merge zizzer:/bk/sparcfsLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5 --HG-- extra : convert_revision : c6d174716641f0b8286b8478bcb9053b3eec54e3
2006-12-12Merge zizzer:/bk/newmemLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5 --HG-- extra : convert_revision : 6e58629b1e51f1fc493a89f16c3f2e676dc5d191
2006-12-12Merge zizzer:/bk/newmem/Gabe Black
into zower.eecs.umich.edu:/eecshome/m5/newmem --HG-- extra : convert_revision : 17d6c49ee15af5d192dedf82871159219d4277cd
2006-12-12Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/test-regress --HG-- extra : convert_revision : d420ee86454b72b0e5d3a98bac3b496f172c1788
2006-12-12Fix bugs in tlbmap (and thus rangemap since the code is nearly identical)Ali Saidi
Deal with block initializing stores (by doing nothing, at some point we might want to do the write hint 64 like thing) Fix tcc instruction igoner in legion-lock stuff to be correct in all cases Have console interrupts warn rather than panicing until we figure out what to do with interrupts src/arch/sparc/miscregfile.cc: src/arch/sparc/miscregfile.hh: add a magic miscreg which reads all the bits the tlb needs in one go src/arch/sparc/tlb.cc: initialized the context type and id to reasonable values and handle block init stores src/arch/sparc/tlb_map.hh: fix bug in tlb map code src/base/range_map.hh: fix bug in rangemap code and add range_multimap (these are probably useful for bus range stuff) src/cpu/exetrace.cc: fixup tcc ignore code to be correct src/dev/sparc/t1000.cc: make console interrupt stuff warn instead of panicing until we get interrupt stuff figured out src/unittest/rangemaptest.cc: fix up the rangemap unit test to catch the missing case --HG-- extra : convert_revision : 70604a8b5d0553aa0b0bd7649f775a0cfa8267a5
2006-12-12Allow for multiple redirects to happen on a single cycle (only the one for ↵Kevin Lim
the oldest instruction is passed on to commit). This fixes a minor bug when multiple FU completions come back out of order (due to the order in which the FUs are freed up), and the oldest redirect isn't recorded properly. The eon benchmark should run now. src/cpu/o3/iew_impl.hh: Allow for multiple redirects to happen on a single cycle (only the one for the oldest instruction is passed on to commit). --HG-- extra : convert_revision : b7d202dee1754539ed814f0fac59adb8c6328ee1
2006-12-12Rename the StaticInst-based (read|set)(Int|Float)Reg methods to ↵Steve Reinhardt
(read|set)(Int|Float)RegOperand to distinguish from non-StaticInst version. --HG-- extra : convert_revision : b33ce0ebe2fee86cc791c00a35d8c6e395e1380c
2006-12-12Get rid of unused lock code.Steve Reinhardt
--HG-- extra : convert_revision : a8030132268662ca54f487b8d32d09ba224317a8
2006-12-11Fix up in case a req hasn't yet been generated for this instruction (if ↵Kevin Lim
there was a fault prior to translation). --HG-- extra : convert_revision : 43f4ea5e6a234cc6071006eab72135c11b8523c8
2006-12-11Fix for fetch to use the icache's block size to generate proper access size.Kevin Lim
--HG-- extra : convert_revision : 0f292233ac05b584f527c32f80e3ca3d40a6a2c1
2006-12-09Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
into vm1.(none):/home/stever/bk/newmem-cache2 --HG-- extra : convert_revision : e1ed5c8edb95e99200b4d26317f55f71338a96df
2006-12-09fix lisa's hand mergeAli Saidi
--HG-- extra : convert_revision : d25604156ae0b2cf29d92fb960b8f5d77427985b
2006-12-09Merge zizzer:/bk/sparcfsAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : c51fd95f7acd7cffb3ea705d7216772f0a801844
2006-12-09Allocate the correct number of global registersAli Saidi
Fix fault formating and code for traps fix a couple of bugs in the decoder Cleanup/fix page table entry code Implement more mmaped iprs, fix numbered tlb insertion code, add function to dump tlb contents Don't panic if we differ from legion on a tcc instruction because of where legion prints its data and where we print our data src/arch/sparc/faults.cc: Fix fault formating and code for traps src/arch/sparc/intregfile.hh: allocate the correct number of global registers src/arch/sparc/isa/decoder.isa: fix a couple of bugs in the decoder: wrasi should write asi not ccr, done/retry should get hpstate from htstate src/arch/sparc/pagetable.hh: cleanup/fix page table code src/arch/sparc/tlb.cc: implement more mmaped iprs, fix numbered insertion code, add function to dump tlb contents src/arch/sparc/tlb.hh: add functions to write TagAccess register on tlb miss and to dump all tlb entries for debugging src/cpu/exetrace.cc: dump tlb entries on error, don't consider differences the cycle we take a trap to be bad. --HG-- extra : convert_revision : d7d771900f6f25219f3dc6a6e51986d342a32e03
2006-12-08Merge zizzer:/bk/sparcfsLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5 src/arch/sparc/ua2005.cc: hand merge --HG-- extra : convert_revision : 5157fa5d7053cb93f73241c63871eaae6f58b8a6
2006-12-08mostly implemented SOFTINT relevant interrupt stuff.Lisa Hsu
src/arch/sparc/interrupts.hh: add in thread_context.hh to get access to tc. get rid of stubs that don't make sense right now. implement checking and get softint interrupts src/arch/sparc/miscregfile.cc: softint should be OR-ed on a write. src/arch/sparc/miscregfile.hh: add some enums for state fields for easy access to bitmasks of HPSTATE and PSTATE regs. src/arch/sparc/ua2005.cc: implement writing SOFTINT, PSTATE, PIL, and HPSTATE properly, add helpful info to panic for bad reg write. --HG-- extra : convert_revision : d12d1147b508121075ee9be4599693554d4b9eae
2006-12-07Fixed to take into account the misc regs that became int regs.Gabe Black
--HG-- extra : convert_revision : b4f78f6e48fdd2f1774ba63b28615e0d2556b7b9
2006-12-07get legion/m5 to first tlb miss faultAli Saidi
src/arch/sparc/asi.cc: src/arch/sparc/asi.hh: add sparc error asi src/arch/sparc/faults.cc: put a panic in if TL == MaxTL src/arch/sparc/isa/decoder.isa: Hpstate needs to be updated on a done too src/arch/sparc/miscregfile.cc: warn istead of panicing of fprs/fsr accesses src/arch/sparc/tlb.cc: add sparc error register code that just does nothing fix a couple of other tlb bugs src/arch/sparc/ua2005.cc: fix implementation of HPSTATE write src/cpu/exetrace.cc: let exectrate mess up a couple of times before dying src/python/m5/objects/T1000.py: add l2 error status register fake devices --HG-- extra : convert_revision : ed5dfdfb28633bf36e5ae07d244f7510a02874ca
2006-12-07Compilation fixesGabe Black
--HG-- extra : convert_revision : 974e91a960251a35d5ebb76c7e6c7ac330339896
2006-12-07Fix for squashing during a serializing instruction.Gabe Black
--HG-- extra : convert_revision : 04f9131258bfb7cca1654e00273edb29bde2366b
2006-12-07Make branches handle the lack of a symbol table or the lack of a symbol ↵Gabe Black
gracefully. --HG-- extra : convert_revision : 7bb16405999b86f9fa082a6d44da43d346edc182
2006-12-07Change how Page Faults work in SPARC. It now prints the faulting address, ↵Gabe Black
and panics instead of fatals. This isn't technically what it should do, but it makes gdb stop at the panic rather than letting m5 exit. --HG-- extra : convert_revision : 3b14c99edaf649e0809977c9579afb2b7b0d72e9
2006-12-06Handle access to ASI_QUEUEAli Saidi
Add function for interrupt ASIs add all the new MISCREGs to the copyMiscRegs() file src/arch/sparc/asi.cc: src/arch/sparc/asi.hh: Add function for interrupt ASIs src/arch/sparc/miscregfile.cc: src/arch/sparc/miscregfile.hh: Add QUEUE asi/misc registers src/arch/sparc/regfile.cc: add all the new MISCREGs to the copyMiscRegs() file src/arch/sparc/tlb.cc: Handle access to ASI_QUEUE --HG-- extra : convert_revision : 7a14450485816e6ee3bc8c80b462a13e1edf0ba0
2006-12-06Many more fixes for SPARC_FS. Gets us to the point where SOFTINT startsAli Saidi
getting touched. configs/common/FSConfig.py: Physical memory on the T1 starts at 1MB, The first megabyte is unmapped to catch bugs src/arch/isa_parser.py: we should readmiscregwitheffect not readmiscreg src/arch/sparc/asi.cc: Fix AsiIsNucleus spelling with respect to header file Add ASI_LSU_CONTROL_REG to AsiSiMmu src/arch/sparc/asi.hh: Fix spelling of two ASIs src/arch/sparc/isa/decoder.isa: switch back to defaults letting the isa_parser insert readMiscRegWithEffect src/arch/sparc/isa/formats/mem/util.isa: Flesh out priviledgedString with hypervisor checks Make load alternate set the flags correctly src/arch/sparc/miscregfile.cc: insert some forgotten break statements src/arch/sparc/miscregfile.hh: Add some comments to make it easier to find which misc register is which number src/arch/sparc/tlb.cc: flesh out the tlb memory mapped registers a lot more src/base/traceflags.py: add an IPR traceflag src/mem/request.hh: Fix a bad assert() in request --HG-- extra : convert_revision : 1e11aa004e8f42c156e224c1d30d49479ebeed28
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