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2006-10-10Two minor fixes.Kevin Lim
configs/common/SysPaths.py: Undo accidental change. src/SConscript: Fix. --HG-- extra : convert_revision : 665b186cff7d8ae560601ced7ae407a41a16cfea
2006-10-09Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem src/cpu/memtest/memtest.cc: src/cpu/memtest/memtest.hh: src/cpu/simple/timing.hh: tests/configs/o3-timing-mp.py: Hand merge. --HG-- extra : convert_revision : a58cc439eb5e8f900d175ed8b5a85b6c8723e558
2006-10-09Comment out code that messed up SMT (but will be needed eventually).Kevin Lim
src/cpu/o3/cpu.cc: Comment out reseting CPU structures for now. This can be updated to work in the future. --HG-- extra : convert_revision : bc1a86e2fe47da5acb14ba8b64568b0355431f1c
2006-10-09Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus --HG-- extra : convert_revision : 2adde42edead2cedeeba60cc0d2697a2d58682be
2006-10-09Fix a typo preventing compilationRon Dreslinski
--HG-- extra : convert_revision : 9158d81231cd1d083393576744ce80afd0b74867
2006-10-09Fix how upgrades work.Ron Dreslinski
Remove some dead code. src/mem/cache/cache_impl.hh: Upgrades don't need a response. Moved satisfied check into bus so removed some dead code. src/mem/cache/coherence/coherence_protocol.cc: src/mem/packet.hh: Upgrades don't require a response --HG-- extra : convert_revision : dee0440ff19ba4c9e51bf9a47a5b0991265cfc1d
2006-10-09Be sure to delete packet and sender state if the cache is blocked.Kevin Lim
src/cpu/o3/lsq_unit.hh: Be sure to delete data if the cache is blocked. --HG-- extra : convert_revision : fafbcfb8937e85555823942e69e798e557a600e5
2006-10-09Fix caches plus sampling switch over.Kevin Lim
src/cpu/o3/cpu.cc: Fix up caches plus sampling switch over. --HG-- extra : convert_revision : 49d0c16d4c5e8d5ba83749d568a4efe3b42e3a97
2006-10-09One step closet to having NACK's work.Ron Dreslinski
src/cpu/memtest/memtest.cc: Fix functional return path src/cpu/memtest/memtest.hh: Add snoop ranges in src/mem/cache/base_cache.cc: Properly signal NACKED src/mem/cache/cache_impl.hh: Catch nacked packet and panic for now --HG-- extra : convert_revision : 59a64e82254dfa206681c5f987e6939167754d67
2006-10-09Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus --HG-- extra : convert_revision : 8267487b935eaf11665841ace3a5c664751b53b0
2006-10-09Potentially functional partially timed bandwidth limitted bus model.Gabe Black
src/mem/bus.cc: Fixes to the previous hand merging, and put the snooping back into recvTiming and out of it's own function. src/mem/bus.hh: Put snooping back into recvTiming and not in it's own function. --HG-- extra : convert_revision : fd031b7e6051a5be07ed6926454fde73b1739dc6
2006-10-09Fix a typo in the printfRon Dreslinski
--HG-- extra : convert_revision : bfa8ffae0a9bef25ceca168ff376ba816abf23f3
2006-10-09Fix a bitwise operation that was accidentally a logical operation.Ron Dreslinski
--HG-- extra : convert_revision : 30f64bcb6bea47fd8cd6d77b0df17eff04dbbad0
2006-10-09Make memtest work with 8 memtestersRon Dreslinski
src/mem/physical.cc: Update comment to match memtest use src/python/m5/objects/PhysicalMemory.py: Make memtester have a way to connect functionally tests/configs/memtest.py: Properly create 8 memtesters and connect them to the memory system --HG-- extra : convert_revision : e5a2dd9c8918d58051b553b5c6a14785d48b34ca
2006-10-09Merge zizzer:/z/m5/Bitkeeper/newmemRon Dreslinski
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest --HG-- extra : convert_revision : b4cb1702ffa2fca298cfde47683cac019e1da900
2006-10-09Add more DPRINTF's fix a supply condition.Ron Dreslinski
src/mem/cache/cache_impl.hh: Add more usefull DPRINTF's REmove the PC to get rid of asserts --HG-- extra : convert_revision : 3f6d832b138d058dbe79bb5f42bd2db9c50b35b5
2006-10-09Set size properly on uncache accessesRon Dreslinski
Don't use the senderState after you get a succesful sendTiming. Not guarnteed to be correct src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: src/mem/cache/cache.hh: src/mem/cache/cache_impl.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/miss/blocking_buffer.hh: src/mem/cache/miss/miss_queue.hh: Don't use the senderState after you get a succesful sendTiming. Not guarnteed to be correct --HG-- extra : convert_revision : 2e8e812bf7fd3ba2b4cba7f7173cb41862f761af
2006-10-09Fix outstanding bug (FS#158).Kevin Lim
src/cpu/o3/cpu.cc: Extra debugging, fix a bug brought up on bug tracker. --HG-- extra : convert_revision : 23f8b166ba0d0af54e15b651ed28f59a1bc9d2f2
2006-10-09Fix checker bug.Kevin Lim
src/cpu/checker/thread_context.hh: Checker's TC should only copy state, and not fully take over from the old context (prevents it from accidentally stealing the quiesce event). --HG-- extra : convert_revision : 5760f9c5bae749f8d1df35e4c898df13e41b0224
2006-10-09Have cpus send snoop rangesRon Dreslinski
--HG-- extra : convert_revision : 2a1fba141e409ee1d7a0b69b5b21d236e3d4ce68
2006-10-09Put a check in so people know not to create more than 8 memtesters.Ron Dreslinski
--HG-- extra : convert_revision : 41ab297dc681b2601be1df33aba30c39f49466d8
2006-10-09Merge zizzer:/z/m5/Bitkeeper/newmemRon Dreslinski
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest --HG-- extra : convert_revision : 77b06379a520dd91f124c0a543e30ec3a9cd1452
2006-10-09Don't create a response if one isn't needed.Ron Dreslinski
--HG-- extra : convert_revision : 37bd230f527f64eb12779157869aae9dcfdde7fd
2006-10-09Don't block responses even if the cache is blocked.Ron Dreslinski
--HG-- extra : convert_revision : a1558eb55806b2a3e7e63249601df2c143e2235d
2006-10-09Update the Memtester, commit a config file/test for it.Ron Dreslinski
src/cpu/SConscript: Add memtester to the compilation environment. Someone who knows this better should make the MemTest a cpu model parameter. For now attached with the build of o3 cpu. src/cpu/memtest/memtest.cc: src/cpu/memtest/memtest.hh: Update Memtest for new mem system src/python/m5/objects/MemTest.py: Update memtest python description --HG-- extra : convert_revision : d6a63e08fda0975a7abfb23814a86a0caf53e482
2006-10-09Update memory assertion to check for whole range.Kevin Lim
src/mem/physical.cc: Update assertion to check for full range. --HG-- extra : convert_revision : ee815702ba4dd6ae1169c0595c978dd153014c73
2006-10-08Merge zizzer:/bk/newmemLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem --HG-- extra : convert_revision : a0775bf59ff7049b76917b1ab551bc28efd56b3d
2006-10-08post checkpoint restoration the bus ranges need to be re-initialized for ALL ↵Lisa Hsu
pci devs, not just ide. src/dev/ide_ctrl.cc: this range change needs to be done for all pio devices, not just the ide. src/dev/pcidev.cc: range change needs to be done at here, not in the ide_ctrl file. --HG-- extra : convert_revision : 60c65c55e965b02d671dba7aa8793e5a81f40348
2006-10-08add in serialization of AtomicSimpleCPU _status. This is needed because ↵Lisa Hsu
right now unserializing breaks an assert since CPU status is not saved. Kev says that this will break uniform serialization across CPUs since each type of CPU has its own "status" enum set. So, the repercussions are that if you serialize in this CPU, you must first unserialize in this CPU before switching to something else you want. src/cpu/simple/atomic.cc: add in serialization of AtomicSimpleCPU _status. Kev says that this will break uniform serialization across CPUs since each type of CPU has its own "status" enum set. So, the repercussions are that if you serialize in this CPU, you must first unserialize in this CPU before switching to something else you want. --HG-- extra : convert_revision : 7000f660aecea6fef712bf81853d9a7b90d625ee
2006-10-08Fixes for Port proxies and proxy parameters.Steve Reinhardt
--HG-- extra : convert_revision : 76b16fe2926611bd1c12c8ad7392355ad30a5138
2006-10-08Make sure to propogate sendFunctional calls with functional not atomic.Ron Dreslinski
src/mem/cache/cache_impl.hh: Fix a error case by putting a panic in. Make sure to propogate sendFunctional calls with functional not atomic. --HG-- extra : convert_revision : 05d03f729a40cfa3ecb68bcba172eb560b24e897
2006-10-08Fixes for functional path.Ron Dreslinski
If the cpu needs to update any state when it gets a functional write (LSQ??) then that code needs to be written. src/cpu/o3/fetch_impl.hh: src/cpu/o3/lsq_impl.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: CPU's can recieve functional accesses, they need to determine if they need to do anything with them. src/mem/bus.cc: src/mem/bus.hh: Make the fuctional path do the correct tye of snoop --HG-- extra : convert_revision : 70d09f954b907a8aa9b8137579cd2b06e02ae2ff
2006-10-08Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus src/mem/bus.cc: Hand merged. Needs to be fixed --HG-- extra : convert_revision : df03219ccfd18431cc726a063bd29d30554944a1
2006-10-08Only respond if the pkt needs a response.Ron Dreslinski
Fix an issue with memory handling writebacks. src/mem/cache/base_cache.hh: src/mem/tport.cc: Only respond if the pkt needs a response. src/mem/physical.cc: Make physical memory respond to writebacks, set satisfied for invalidates/upgrades. --HG-- extra : convert_revision : 7601987a7923e54a6d1a168def4f8133d8de19fd
2006-10-08Merge zizzer:/z/m5/Bitkeeper/newmemRon Dreslinski
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest --HG-- extra : convert_revision : f3067efb7f3ff30158d541dfc52de4ea8edae576
2006-10-08Move away from using the statusChange function on snoops. Clean up snooping ↵Ron Dreslinski
code in general. --HG-- extra : convert_revision : 5a57bfd7742a212047fc32e8cae0dc602fdc915c
2006-10-08missing elseGabe Black
--HG-- extra : convert_revision : 8fe0e00dc3ae70b4449a78c15dd249939e644f02
2006-10-08bus changesGabe Black
src/mem/bus.cc: src/mem/bus.hh: minor fix and some formatting changes src/python/m5/objects/Bus.py: changed bits to bytes --HG-- extra : convert_revision : dcd22205604b7a2727eaf2094084c4858f3589c5
2006-10-08Replace tests of LOCKED/UNCACHEABLE flags with isLocked()/isUncacheable().Steve Reinhardt
--HG-- extra : convert_revision : f22ce3221d270ecf8631d3dcaed05753accd5461
2006-10-08Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus --HG-- extra : convert_revision : 1749397443ccb320d32f8dd23c71ed0431d30cb7
2006-10-08A possible implementation of a multiplexed bus.Gabe Black
--HG-- extra : convert_revision : 3c560eda12ffd8ca539c91024baf2770b963ede8
2006-10-08Add in HasData, and move the define of NUM_MEM_CMDS to a more visible location.Gabe Black
--HG-- extra : convert_revision : 4379efe892ca0a39363ee04009e1bbb8c8f77afa
2006-10-08Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)Steve Reinhardt
and PhysicalMemory. *No* support for caches or O3CPU. Note that properly setting cpu_id on all CPUs is now required for correct operation. src/arch/SConscript: src/base/traceflags.py: src/cpu/base.hh: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: src/cpu/simple/timing.hh: src/mem/physical.cc: src/mem/physical.hh: src/mem/request.hh: src/python/m5/objects/BaseCPU.py: tests/configs/simple-atomic.py: tests/configs/simple-timing.py: tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing) and PhysicalMemory. *No* support for caches or O3CPU. --HG-- extra : convert_revision : 6ce982d44924cc477e049b9adf359818908e72be
2006-10-08Rename some vars for clarity.Steve Reinhardt
--HG-- extra : convert_revision : 765283ae54d2d6b5885ea44c6c1813d4bcf18488
2006-10-08Allocate new thread stacks and shared mem region via Process page tableSteve Reinhardt
for Tru64 thread library emulation. --HG-- extra : convert_revision : dbd307536e260e24ef79130d2aa88d84e33f03d4
2006-10-08Clean up configs.Kevin Lim
configs/common/FSConfig.py: configs/common/SysPaths.py: configs/example/fs.py: configs/example/se.py: tests/configs/o3-timing-mp.py: tests/configs/o3-timing.py: Clean up configs by removing FullO3Config and instead using default values. src/python/m5/objects/FUPool.py: Add in default FUPool. src/python/m5/objects/O3CPU.py: Use defaults better. Also set checker parameters, and fix up a config bug. --HG-- extra : convert_revision : 5fd0c000143f4881f10a9a575c3810dc97cb290b
2006-10-08Record numCycles properly.Kevin Lim
src/cpu/simple/timing.cc: Record numCycles stat properly. src/cpu/simple/timing.hh: Extra variable to help record numCycles stat. --HG-- extra : convert_revision : 343311902831820264878aad41dc619999726b6b
2006-10-08Updates to O3 CPU. It should now work in FS mode, although sampling still ↵Kevin Lim
has a bug. src/cpu/o3/commit_impl.hh: Fixes for compile and sampling. src/cpu/o3/cpu.cc: Deallocate and activate threads properly. Also hopefully fix being able to use caches while switching over. src/cpu/o3/cpu.hh: Fixes for deallocating and activating threads. src/cpu/o3/fetch_impl.hh: src/cpu/o3/lsq_unit.hh: Handle getting back a BadAddress result from the access. src/cpu/o3/iew_impl.hh: More debug output. src/cpu/o3/lsq_unit_impl.hh: Fixup store conditional handling (still a bit of a hack, but works now). Also handle getting back a BadAddress result from the access. src/cpu/o3/thread_context_impl.hh: Deallocate context now records if the context should be fully removed. --HG-- extra : convert_revision : 55f81660602d0e25367ce1f5b0b9cfc62abe7bf9
2006-10-07Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem --HG-- extra : convert_revision : 0309a453c0d65579cfa022888d1a2ab4f0171a9f
2006-10-07Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem.head --HG-- extra : convert_revision : acab791328d16daace6dfbdc667067ddc68fb6ca
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-16 11:30:16 +0000