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AgeCommit message (Expand)Author
2006-07-27Need config read/write latency.Kevin Lim
2006-07-26MIPS ISA runs 'hello world' in O3CPU ...Korey Sewell
2006-07-26Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2006-07-26Added alot of fp instructions, and some impdep instructions.Gabe Black
2006-07-26Now ignore sigactionGabe Black
2006-07-23Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemKorey Sewell
2006-07-23This changeset gets the MIPS ISA pretty much working in the O3CPU. It builds,...Korey Sewell
2006-07-23Added myself to the authors list.Gabe Black
2006-07-22Fixed subtract with carry, and started some work with floating point.Gabe Black
2006-07-21Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-07-21Minor functionality updates.Kevin Lim
2006-07-20Fixed a glitch in the disassembly output.Gabe Black
2006-07-20Merge m5.eecs.umich.edu:/bk/newmemGabe Black
2006-07-20Merge zizzer:/bk/newmemAli Saidi
2006-07-20Move PioPort timing code into Simple Timing Port objectAli Saidi
2006-07-20Enforce the timing cpu ticking at it's clock rateAli Saidi
2006-07-19Merge zizzer:/bk/newmemAli Saidi
2006-07-19Change the device latency here to a latency rather than a TickAli Saidi
2006-07-19Minor changes to reflect state used for regression stats.Kevin Lim
2006-07-19Put regression tests back into m5. They are located in the "tests" directory...Kevin Lim
2006-07-19Get the path to load the ini file from. I'm not sure if this fix is needed i...Kevin Lim
2006-07-19O3CPU fixes.Kevin Lim
2006-07-19Some minor compiling fixes.Kevin Lim
2006-07-19Cleaned things up a little.Gabe Black
2006-07-18Merge m5.eecs.umich.edu:/bk/newmemGabe Black
2006-07-14Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-07-14Minor updates.Kevin Lim
2006-07-14Fix the CheckerCPU being included via python.Kevin Lim
2006-07-14forgot tidKorey Sewell
2006-07-14For now, halt context is the same as deallocating.Korey Sewell
2006-07-14MIPS specific fixes ... the main thing is that SMT threads get their own stac...Korey Sewell
2006-07-13Merge zizzer:/bk/newmemAli Saidi
2006-07-13fix help when no arguments are passed to m5Ali Saidi
2006-07-13add system.mem_mode = ['timing', 'atomic']Ali Saidi
2006-07-13Move Dcache port creation from LSQUnit to LSQ in order to support Ron's recen...Kevin Lim
2006-07-13Fix for bug when squashing and the fetching. Now fetch checks if the cache d...Kevin Lim
2006-07-13Update for changes to draining.Kevin Lim
2006-07-13Fix help message printing. Might need to clean up the handling of the sys.ex...Kevin Lim
2006-07-12memory mode information now contained in system objectAli Saidi
2006-07-12Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-07-12Be sure to include the EIO sources as well so we can run regression tests.Kevin Lim
2006-07-12Serialization changes to make O3CPU consistent with the other models.Kevin Lim
2006-07-12Push more default options to the Python object level as they are rarely chang...Kevin Lim
2006-07-12Updates for serialization. As long as the tickEvent doesn't need to be seria...Kevin Lim
2006-07-12Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-07-12Track the PC of the cache data stored in fetch so it doesn't access memory mu...Kevin Lim
2006-07-12Add --pdbNathan Binkert
2006-07-12Merge m5.eecs.umich.edu:/bk/newmemNathan Binkert
2006-07-12Fix __file__ for scriptsNathan Binkert
2006-07-11Merge zizzer:/z/m5/Bitkeeper/newmemRon Dreslinski
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