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2012-03-09CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectableGeoffrey Blake
Enables the CheckerCPU to be selected at runtime with the --checker option from the configs/example/fs.py and configs/example/se.py configuration files. Also merges with the SE/FS changes.
2012-03-09ARM: Don't reset CPUs that are going to be switched in.Ali Saidi
2012-03-09System: Move code in initState() back into constructor whenever possible.Ali Saidi
The change to port proxies recently moved code out of the constructor into initState(). This is needed for code that loads data into memory, however for code that setups symbol tables, kernel based events, etc this is the wrong thing to do as that code is only called when a checkpoint isn't being restored from.
2012-03-09ARM: Fix valgrind reported error on O3 that was causing minor stats changes.Ali Saidi
2012-03-09cache: Allow main memory to be at disjoint address ranges.Ali Saidi
2012-03-06build scripts: Made minor modifications to reduce build overhead time.Marc Orr
1. --implicit-cache behavior is default. 2. makeEnv in src/SConscript is conditionally called. 3. decider set to MD5-timestamp 4. NO_HTML build option changed to SLICC_HTML (defaults to False)
2012-03-02DynInst: get rid of dead MyHash code.Steve Reinhardt
Not sure what this was ever used for, but it doesn't seem used anymore.
2012-03-02CPU: Check that the interrupt controller is created when neededAndreas Hansson
This patch adds a creation-time check to the CPU to ensure that the interrupt controller is created for the cases where it is needed, i.e. if the CPU is not being switched in later and not a checker CPU. The patch also adds the "createInterruptController" call to a number of the regression scripts.
2012-03-02Ruby: Rename RubyPort::sendTiming to avoid overriding base classAndreas Hansson
This patch renames the sendTiming member function in the RubyPort to avoid inadvertently hiding Port::sendTiming (discovered through some rather painful debugging). The RubyPort does, in fact, rely on the functionality of the queued port and the implementation merely schedules a send the next cycle. The new name for the member function is sendNextCycle to better reflect this behaviour. In the unlikely event that we ever shift to using C++11 the member functions in Port should have a "final" identifier to prevent any overriding in derived classes.
2012-03-02ARM: FIx a bug preventing multiple cores booting a VExpress_EMM machine.Ali Saidi
New kernel code verifies that multi-processor extensions are available before booting secondary CPUs.
2012-03-01ARM: FIx missing cf controller connection.Ali Saidi
2012-03-01VNC: spacingChander Sudanthi
Fixed some spacing in a switch statement
2012-03-01ARM: Add support for Versatile Express extended memory mapAli Saidi
Also clean up how we create boot loader memory a bit.
2012-03-01ARM: Add RTC device for ARM platforms.Ali Saidi
This change implements a PL031 real time clock. --HG-- rename : src/dev/arm/timer_sp804.cc => src/dev/arm/rtc_pl031.cc rename : src/dev/arm/timer_sp804.hh => src/dev/arm/rtc_pl031.hh
2012-03-01ARM: Add limited CP14 support.Matt Horsnell
New kernels attempt to read CP14 what debug architecture is available. These changes add the debug registers and return that none is currently available.
2012-03-01Cache: Fix an issue with LRU when bonus block is used to complete transaction.Ali Saidi
The block is never inserted because it's the one extra block in the cache, but it can be invalidated twice in a row. In that case the block doesn't have a new master id (beacuse it was never inserted), however it is valid and the accounting goes wrong at that point.
2012-03-01ARM: move kernel func event to correct location.Dam Sunwoo
With the recent series of patches, the symbol table loading moved from "construct" time to "init" time, but the kernel function event callback registration was left behind. This patch moves it to the proper location.
2012-03-01ARM: fix bits-to-fp conversion function declarations.Giacomo Gabrielli
Add extra declarations to allow the compiler to pick up the right function. Please note that these declarations have been added as part of the clang-related changes.
2012-03-01x86: Fix x86 TLB and WalkerNilay Vaish
This patch adds a function to X86 tlb that returns the walker port. This port is required for correctly connecting the walker ports for the cpu just switched in
2012-03-01x86: Fix switching of CPUsNilay Vaish
This patch prevents creation of interrupt controller for cpus that will be switched in later
2012-02-29MEM: Make all the port proxy members constAndreas Hansson
This is a trivial patch that merely makes all the member functions of the port proxies const. There is no good reason why they should not be, and this change only serves to make it explicit that they are not modified through their use.
2012-02-29SWIG: Ensure ptrdiff_t is a known type in gcc >= 4.6.1Andreas Hansson
This patch fixes a compilation error that occurs with gcc >= 4.6.1, caused by swig not including cstddef and not using the std:: namespace prefix for ptrdiff_t. There is an old patch, http://reviews.m5sim.org/r/913/ that no longer applies cleanly and this might be re-iterating the same issue. We work around the problem by always enforcing the inclusion of cstddef in all swig interface declarations, and also by explicitly using std::ptrdiff_t.
2012-02-26X86: Use the M5PanicFault fault in execute methods instead of calling panic.Gabe Black
If an instruction is executed speculatively and hits a situation where it wants to panic, it should return a fault instead. If the instruction was misspeculated, the fault can be thrown away. If the instruction wasn't misspeculated, the fault will be invoked and the panic will still happen.
2012-02-24MEM: Simplify cache ports preparing for master/slave splitAndreas Hansson
This patch splits the two cache ports into a master (memory-side) and slave (cpu-side) subclass of port with slightly different functionality. For example, it is only the CPU-side port that blocks incoming requests, and only the memory-side port that schedules send events outside of what the transmit list dictates. This patch simplifies the two classes by relying further on SimpleTimingPort and also generalises the latter to better accommodate the changes (introducing trySendTiming and scheduleSend). The memory-side cache port overrides sendDeferredPacket to be able to not only send responses from the transmit list, but also send requests based on the MSHRs. A follow on patch further simplifies the SimpleTimingPort and the cache ports.
2012-02-24MEM: Prepare mport for master/slave splitAndreas Hansson
This patch simplifies the mport in preparation for a split into a master and slave role for the message ports. In particular, sendMessageAtomic was only used in a single location and similarly so sendMessageTiming. The affected interrupt device is updated accordingly.
2012-02-24Ruby: Simplify tester ports by not using SimpleTimingPortAndreas Hansson
This patch simplfies the master ports used by RubyDirectedTester and RubyTester by avoiding the use of SimpleTimingPort. Neither tester made any use of the functionality offered by SimpleTimingPort besides a trivial implementation of recvFunctional (only snoops) and recvRangeChange (not relevant since there is only one master). The patch does not change or add any functionality, it merely makes the introduction of a master/slave port easier (in a future patch).
2012-02-24MEM: Move all read/write blob functions from Port to PortProxyAndreas Hansson
This patch moves the readBlob/writeBlob/memsetBlob from the Port class to the PortProxy class, thus making a clear separation of the basic port functionality (recv/send functional/atomic/timing), and the higher-level functional accessors available on the port proxies. There are only a few places in the code base where the blob functions were used on ports, and they are all for peeking into the memory system without making a normal memory access (in the memtest, and the malta and tsunami pchip). The memtest also exemplifies how easy it is to create a non-translating proxy if desired. The malta and tsunami pchip used a slave port to perform a functional read, and this is now changed to rely on the physProxy of the system (to which they already have a pointer).
2012-02-24MEM: Make port proxies use references rather than pointersAndreas Hansson
This patch is adding a clearer design intent to all objects that would not be complete without a port proxy by making the proxies members rathen than dynamically allocated. In essence, if NULL would not be a valid value for the proxy, then we avoid using a pointer to make this clear. The same approach is used for the methods using these proxies, such as loadSections, that now use references rather than pointers to better reflect the fact that NULL would not be an acceptable value (in fact the code would break and that is how this patch started out). Overall the concept of "using a reference to express unconditional composition where a NULL pointer is never valid" could be done on a much broader scale throughout the code base, but for now it is only done in the locations affected by the proxies.
2012-02-24MEM: Move port creation to the memory object(s) constructionAndreas Hansson
This patch moves all port creation from the getPort method to be consistently done in the MemObject's constructor. This is possible thanks to the Swig interface passing the length of the vector ports. Previously there was a mix of: 1) creating the ports as members (at object construction time) and using getPort for the name resolution, or 2) dynamically creating the ports in the getPort call. This is now uniform. Furthermore, objects that would not be complete without a port have these ports as members rather than having pointers to dynamically allocated ports. This patch also enables an elaboration-time enumeration of all the ports in the system which can be used to determine the masterId.
2012-02-24CPU: Round-two unifying instr/data CPU ports across modelsAndreas Hansson
This patch continues the unification of how the different CPU models create and share their instruction and data ports. Most importantly, it forces every CPU to have an instruction and a data port, and gives these ports explicit getters in the BaseCPU (getDataPort and getInstPort). The patch helps in simplifying the code, make assumptions more explicit, andfurther ease future patches related to the CPU ports. The biggest changes are in the in-order model (that was not modified in the previous unification patch), which now moves the ports from the CacheUnit to the CPU. It also distinguishes the instruction fetch and load-store unit from the rest of the resources, and avoids the use of indices and casting in favour of keeping track of these two units explicitly (since they are always there anyways). The atomic, timing and O3 model simply return references to their already existing ports.
2012-02-24MEM: Fatal when no port can be found for an addressAndreas Hansson
This patch adds a check in the findPort method to ensure that an invalid port id is never returned. Previously this could happen if no default port was set, and no address matched the request, in which case -1 was returned causing a SEGFAULT when using the id to index in the port array. To clean things up further a symbolic name is added for the invalid port id.
2012-02-20SimObject: make get_config_as_dict() tolerate undefined paramsSteve Reinhardt
Without this patch, undefined params cause a cryptic KeyError in multidict inside get_config_as_dict(). This patch lets undefined params through get_config_as_dict() so they can once again generate meaningful error messages later on in the configuration process.
2012-02-14MEM: Fix residual bus ports and make them master/slaveAndreas Hansson
This patch cleans up a number of remaining uses of bus.port which is now split into bus.master and bus.slave. The only non-trivial change is the memtest where the level building now has to be aware of the role of the ports used in the previous level.
2012-02-13BPred: Fix RAS to handle predicated call/return instructions.Mrinmoy Ghosh
Change RAS to fix issues with predicated call/return instructions. Handled all cases in the life of a predicated call and return instruction.
2012-02-13BP: Fix several Branch Predictor issues.Mrinmoy Ghosh
1. Updates the Branch Predictor correctly to the state just after a mispredicted branch, if a squash occurs. 2. If a BTB does not find an entry, the branch is predicted not taken. The global history is modified to correctly reflect this prediction. 3. Local history is now updated at the fetch stage instead of execute stage. 4. In the Update stage of the branch predictor the local predictors are now correctly updated according to the state of local history during fetch stage. This patch also improves performance by as much as 17% on some benchmarks
2012-02-13MEM: Explicit ports and Python binding on CopyEngineAndreas Hansson
The copy-engine ports were previously created implicitly and bound based on the dma port peer rather than relying on the normal Python binding (connectPorts) being called explicitly. This patch makes the copy engine port similar to all other ports in that they are visibly in the Python class and bound using the normal explicit calls through Python.
2012-02-13MEM: Pass the ports from Python to C++ using the Swig paramsAndreas Hansson
This patch adds basic information about the ports in the parameter classes to be passed from the Python world to the corresponding C++ object. Currently, the only information passed is the number of connected peers, which for a Port is either 0 or 1, and for a VectorPort reflects the size of the VectorPort. The default port of the bus had to be renamed to avoid using the name "default" as a field in the parameter class. It is possible to extend the Swig'ed information further and add e.g. a pair with a description and size.
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
This patch classifies all ports in Python as either Master or Slave and enforces a binding of master to slave. Conceptually, a master (such as a CPU or DMA port) issues requests, and receives responses, and conversely, a slave (such as a memory or a PIO device) receives requests and sends back responses. Currently there is no differentiation between coherent and non-coherent masters and slaves. The classification as master/slave also involves splitting the dual role port of the bus into a master and slave port and updating all the system assembly scripts to use the appropriate port. Similarly, the interrupt devices have to have their int_port split into a master and slave port. The intdev and its children have minimal changes to facilitate the extra port. Note that this patch does not enforce any port typing in the C++ world, it merely ensures that the Python objects have a notion of the port roles and are connected in an appropriate manner. This check is carried when two ports are connected, e.g. bus.master = memory.port. The following patches will make use of the classifications and specialise the C++ ports into masters and slaves.
2012-02-12X86: open flags: Another patch from Vince WeaverGabe Black
2012-02-12cpu: add separate stats for insts/ops both globally and per cpu modelAnthony Gutierrez
2012-02-12mem: fix cache stats to use request ids correctlyDam Sunwoo
This patch fixes the cache stats to use the new request ids. Cache stats also display the requestor names in the vector subnames. Most cache stats now include "nozero" and "nonan" flags to reduce the amount of excessive cache stat dump. Also, simplified incMissCount()/incHitCount() functions.
2012-02-12mem: Add a master ID to each request object.Ali Saidi
This change adds a master id to each request object which can be used identify every device in the system that is capable of issuing a request. This is part of the way to removing the numCpus+1 stats in the cache and replacing them with the master ids. This is one of a series of changes that make way for the stats output to be changed to python.
2012-02-12prefetcher: Make prefetcher a sim object instead of it being a parameter on ↵Mrinmoy Ghosh
cache
2012-02-11SPARC: Make PSTATE and HPSTATE a BitUnion.Gabe Black
This gets rid of cryptic bits of code with lots of bit manipulation, and makes some comments redundant.
2012-02-10Ruby: Remove isTagPresent() calls from Sequencer.ccNilay Vaish
This patch removes the calls to isTagPresent() from Sequencer.cc. These calls are made just for setting the cache block to have been most recently used. The calls have been folded in to the function setMRU().
2012-02-10MESI: Add queues for stalled requestsNilay Vaish
This patch adds support for stalling the requests queued up at different controllers for the MESI CMP directory protocol. Earlier the controllers would recycle the requests using some fixed latency. This results in younger requests getting serviced first at times, and can result in starvation. Instead all the requests that need a particular block to be in a stable state are moved to a separate queue, where they wait till that block returns to a stable state and then they are processed.
2012-02-10sim/system: initialize the pagePtr variableNilay Vaish
2012-02-10O3 CPU: Improve handling of delayed commit flagNilay Vaish
The delayed commit flag is used in conjunction with interrupt pending flag to figure out whether or not fetch stage should get more instructions. This patch clears this flag when instructions are squashed. Also, in case an interrupt is pending, currently it is not possible to access the instruction cache. This patch allows accessing the cache in case this flag is set.
2012-02-10O3 CPU: Strengthen condition for handling interruptsNilay Vaish
The condition for handling interrupts is to check whether or not the cpu's instruction list is empty. As observed, this can lead to cases in which even though the instruction list is empty, interrupts are handled when they should not be. The condition is being strengthened so that interrupts get handled only when the last committed microop did not had IsDelayedCommit set.
2012-02-10O3 CPU: Provide the squashing instructionNilay Vaish
This patch adds a function to the ROB that will get the squashing instruction from the ROB's list of instructions. This squashing instruction is used for figuring out the macroop from which the fetch stage should fetch the microops. Further, a check has been added that if the instructions are to be fetched from the cache maintained by the fetch stage, then the data in the cache should be valid and the PC of the thread being fetched from is same as the address of the cache block.