summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Expand)Author
2013-04-23sim: Fix two bugs relating to software caching of PageTable entries.Mitch Hayenga
2013-04-23cpu: Fix TraceGen flag initalisationAndreas Hansson
2013-04-23ruby: mesi coherence protocol: remove unused state M_MBNilay Vaish
2013-04-23x86: increment the stack pointer in lret instChristian Menard
2013-04-23ruby: patch checkpoint restore with garnetNilay Vaish
2013-04-22mem: Address mapping with fine-grained channel interleavingAndreas Hansson
2013-04-22mem: More descriptive enum names for address mappingAndreas Hansson
2013-04-22cpu: Use request flags in trace playbackAndreas Hansson
2013-04-22cpu: Make the generators usable outside the TrafficGen moduleAndreas Hansson
2013-04-22mem: Add a WideIO DRAM configurationAndreas Hansson
2013-04-22mem: Adding verbose debug output in the memory systemUri Wiener
2013-04-22mem: Replace check with panic where inhibited should not happenAndreas Hansson
2013-04-22kvm: Add support for pseudo-ops on ARMAndreas Sandberg
2013-04-22sim: Add a helper function to execute pseudo instructionsAndreas Sandberg
2013-04-22kvm: Add support for state dumping on ARMAndreas Sandberg
2013-04-22kvm: Add basic support for ARMAndreas Sandberg
2013-04-22arm: Add a method to query interrupt state ignoring CPSR masksAndreas Sandberg
2013-04-22kvm: Add experimental support for a perf-based execution timerAndreas Sandberg
2013-04-22kvm: Avoid synchronizing the TC on every KVM exitAndreas Sandberg
2013-04-22kvm: Basic support for hardware virtualized CPUsAndreas Sandberg
2013-04-22cpu: Let python scripts obtain the number of instructions executedTimothy M. Jones
2013-04-22arm: Enable support for triggering a sim panic on kernel panicsAndreas Sandberg
2013-04-22sim: separate nextCycle() and clockEdge() in clockedObjectsDam Sunwoo
2013-04-22cpu: generate SimPoint basic block vector profilesDam Sunwoo
2013-04-22ARM: Add support for HDLCD controller for TC2 and newer Versatile Express tiles.Chris Emmons
2013-04-22sim: Add helper functions that add PCEvents with custom argumentsAndreas Sandberg
2013-04-22cpu: fix a switching issue with the o3 cpu.Ali Saidi
2013-04-17Merged c22628fa2564 and 2285b98847d7Nilay Vaish
2013-04-17base: load weak symbols from object fileDeyuan Guo ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2013-04-17arm: set ldr_ret_uop as conditional or unconditional controlNathanael Premillieu
2013-04-17ruby: moesi cmp directory: add copyright noticeNilay Vaish
2013-04-17dev: Fix a bug in the use of seekp/seekgAndreas Hansson
2013-04-09Ruby: Fix RubyPort evict packet memory leakJoel Hestness
2013-04-09Ruby: Delete packet requests during warmupJoel Hestness
2013-04-09Ruby: Add field to slicc machine for generic typeJoel Hestness
2013-04-09Ruby: Order profilers based on versionJoel Hestness
2013-04-09Ruby: More descriptive message buffer connection fatalJason Power
2013-04-09Ruby: Fix typo in Slicc if-statement AST errorJason Power
2013-04-07Ruby System, Cache Recorder: Use delete [] for trace varsJoel Hestness
2013-03-29o3cpu: commit: changes interrupt handlingNilay Vaish
2013-03-28x86: changes to apic, keyboardNilay Vaish
2013-03-27mem: Fix cache latency bugMitch Hayenga
2013-03-27scons: don't die on warnings in swig-generated codeSteve Reinhardt
2013-03-26mem: Cancel cache retry event when blocking portRene de Jong
2013-03-26mem: Separate waiting for the bus and waiting for a peerAndreas Hansson
2013-03-26mem: Introduce a variable for the retrying portAndreas Hansson
2013-03-26mem: Add a generic id field to the packet traceAndreas Hansson
2013-03-26mem: Add optional request flags to the packet traceAndreas Hansson
2013-03-26cpu: Remove CpuPort and use MasterPort in the CPU classesAndreas Hansson
2013-03-22ruby: slicc: set sender, receiver clock objs for optional queueNilay Vaish
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-30 22:25:13 +0000