summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2010-08-23ARM: Make sure that software prefetch instructions can't change the state of ↵Gene Wu
the TLB
2010-08-23ARM: Don't write tracedata on writes, it might have been freed already.Gene Wu
2010-08-23ARM: Implement CLREX init/complete acc methodsGene Wu
2010-08-23ARM: Fix Uncachable TLB requests and decoding of xn bitGene Wu
2010-08-23Devices: Allow a device to specify that a request is uncachable.Gene Wu
2010-08-23ARM: For non-cachable accesses set the UNCACHABLE flagGene Wu
2010-08-23ARM: Implement DSB, DMB, ISBGene Wu
2010-08-23ARM: Get SCTLR TE bit from reset SCTLRGene Wu
2010-08-23ARM: Implement CLREXGene Wu
2010-08-23ARM: BX instruction can be contitional if last instruction in a IT blockGene Wu
Branches are allowed to be the last instuction in an IT block. Before it was assumed that they could not. So Branches in thumb2 were Uncond.
2010-08-23CPU: Print out flatten-out register index as with IntRegs/FloatRegs traceflagMin Kyu Jeong
2010-08-23CPU: Make Exec trace to print predication result (if false) for memory ↵Min Kyu Jeong
instructions
2010-08-23ARM: mark msr/mrs instructions as SerializeBefore/AfterMin Kyu Jeong
Since miscellaneous registers bypass wakeup logic, force serialization to resolve data dependencies through them * * * ARM: adding non-speculative/serialize flags for instructions change CPSR
2010-08-23O3: Handle loads when the destination is the PC.Min Kyu Jeong
For loads that PC is the destination, check if the load was mispredicted again when the value being loaded returns from memory
2010-08-23ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate.Min Kyu Jeong
THis allows the CPU to handle predicated-false instructions accordingly. This particular patch makes loads that are predicated-false to be sent straight to the commit stage directly, not waiting for return of the data that was never requested since it was predicated-false.
2010-08-23ARM: adding genMachineCheckFault() stub for ARM that doesn't panicMin Kyu Jeong
2010-08-23ARM: DFSR status value for sync external data abort is expected to be 0x8 in ↵Gene Wu
ARMv7
2010-08-23ARM: Temporary local variables can't conflict with isa parser operands.Gene Wu
PC is an operand, so we can't have a temp called PC
2010-08-23ARM: Exclusive accesses must be double word alignedAli Saidi
2010-08-23ARM: Add some registers for big loads/stores to support neon.Ali Saidi
2010-08-23ARM: Decode neon memory instructions.Ali Saidi
2010-08-23ARM: Clean up the ISA desc portion of the ARM memory instructions.Gabe Black
2010-08-23Loader: Don't insert symbols into the symbol table that begin wiht '$'.Ali Saidi
2010-08-23ARM: We don't currently support ThumbEE exceptions, so don't report that we doAli Saidi
2010-08-23ARM: Change how the AMBA device ID checking is done to make it more genericAli Saidi
2010-08-23ARM: Add system for ARM/Linux and bootstrappingAli Saidi
2010-08-23ARM: Add I/O devices for booting linuxAli Saidi
--HG-- rename : src/dev/arm/Versatile.py => src/dev/arm/RealView.py rename : src/dev/arm/versatile.cc => src/dev/arm/realview.cc rename : src/dev/arm/versatile.hh => src/dev/arm/realview.hh
2010-08-23ARM: Implement some more misc registersAli Saidi
2010-08-23ARM: Fix an un-initialized variable bugAli Saidi
2010-08-23Loader: Use address mask provided to load*Symbols when loading the symbols ↵Ali Saidi
from the symbol table.
2010-08-23Loader: Make the load address mask be a parameter of the system rather than ↵Ali Saidi
a constant. This allows one two different OS requirements for the same ISA to be handled. Some OSes are compiled for a virtual address and need to be loaded into physical memory that starts at address 0, while other bare metal tools generate images that start at address 0.
2010-08-23ARM: Finish the timing translation when taking a fault.Min Kyu Jeong
2010-08-23ARM: Use a stl queue for the table walker stateDam Sunwoo
2010-08-23CPU: Set a default value when readBytes faults.Ali Saidi
This was being done in read(), but if readBytes was called directly it wouldn't happen. Also, instead of setting the memory blob being read to -1 which would (I believe) require using memset with -1 as a parameter, this now uses bzero. It's hoped that it's more specialized behavior will make it slightly faster.
2010-08-23Compiler: Fixes for GCC 4.5.Ali Saidi
2010-08-23BASE: Fix genrand to generate both 0s and 1s when max equals one.Ali Saidi
previously was only generating 0s.
2010-08-23stats: Fix off-by-one error in distributions.Ali Saidi
bkt size isn't evenly divisible by max-min and it would round down, it's possible to sample a distribution and have no place to put the sample. When this case occured the simulator would assert.
2010-08-22X86: Get rid of unused file arguments.hh.Gabe Black
2010-08-22SPARC: Fix some style issues in utility.hh.Gabe Black
2010-08-22X86: Get rid of the unused getAllocator on the python base microop class.Gabe Black
This function is always overridden, and doesn't actually have the right signature.
2010-08-20ruby: Added merge GETS optimization to hammerBrad Beckmann
Added an optimization that merges multiple pending GETS requests into a single request to the owner node.
2010-08-20ruby: Fixed minor bug in ruby test for setting the request typeBrad Beckmann
2010-08-20ruby: Stall and wait input messages instead of recyclingBrad Beckmann
This patch allows messages to be stalled in their input buffers and wait until a corresponding address changes state. In order to make this work, all in_ports must be ranked in order of dependence and those in_ports that may unblock an address, must wake up the stalled messages. Alot of this complexity is handled in slicc and the specification files simply annotate the in_ports. --HG-- rename : src/mem/slicc/ast/CheckAllocateStatementAST.py => src/mem/slicc/ast/StallAndWaitStatementAST.py rename : src/mem/slicc/ast/CheckAllocateStatementAST.py => src/mem/slicc/ast/WakeUpDependentsStatementAST.py
2010-08-20ruby: Recycle latency fix for hammerBrad Beckmann
Patch allows each individual message buffer to have different recycle latencies and allows the overall recycle latency to be specified at the cmd line. The patch also adds profiling info to make sure no one processor's requests are recycled too much.
2010-08-20MOESI_hammer: break down miss latency stalled cyclesBrad Beckmann
This patch tracks the number of cycles a transaction is delayed at different points of the request-forward-response loop.
2010-08-20ruby: added probe filter support to hammerBrad Beckmann
2010-08-20ruby: fixed DirectoryMemory's numa_high_bit configurationBrad Beckmann
This fix includes the off-by-one bit selection bug for numa mapping.
2010-08-20ruby: Reset ruby stats in RubySystem unserializeBrad Beckmann
The main purpose for clearing stats in the unserialize process is so that the profiler can correctly set its start time to the unserialized value of curTick.
2010-08-20ruby: Disable migratory sharing for token and hammerBrad Beckmann
This patch allows one to disable migratory sharing for those cache blocks that are accessed by atomic requests. While the implementations are different between the token and hammer protocols, the motivation is the same. For Alpha, LLSC semantics expect that normal loads do not unlock cache blocks that have been locked by LL accesses. Therefore, locked blocks should not transfer write permissions when responding to these load requests. Instead, only they only transfer read permissions so that the subsequent SC access can possibly succeed.
2010-08-20ruby: Added SC fail indication to trace profilingBrad Beckmann