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AgeCommit message (Expand)Author
2011-06-02scons: rename TraceFlags to DebugFlagsNathan Binkert
2011-06-02scons: rename some things from m5 to gem5Nathan Binkert
2011-06-02copyright: Add code for finding all copyright blocks and create a COPYING fileNathan Binkert
2011-06-02copyright: clean up copyright blocksNathan Binkert
2011-06-01SimObject: allow modules in subclass definitionsSteve Reinhardt
2011-05-31orion: bug fix in link power, and some reorgTushar Krishna
2011-05-31garnet: added network ptr to links to be used by orionTushar Krishna
2011-05-29Misc: Remove the URL from warnings, fatals, panics, etc.Gabe Black
2011-05-25Name: Replace M5 with gem5 in a few places it's printed on startup.Gabe Black
2011-05-23sim: style fixes in sim/process.hhSteve Reinhardt
2011-05-23syscall emul: fix Power Linux mmap constant, plus other cleanupSteve Reinhardt
2011-05-23config: revamp x86 config to avoid appending to SimObjectVectorsSteve Reinhardt
2011-05-23config: tweak ruby configs to clean up hierarchySteve Reinhardt
2011-05-23config: reinstate implicit parenting on parameter assignmentSteve Reinhardt
2011-05-23sim: add some DPRINTFs for debugging unserializationSteve Reinhardt
2011-05-23O3: Fix offset calculation into storeQueue buffer for store->load forwardingGeoffrey Blake
2011-05-23O3: Fix issue w/wbOutstading being decremented multiple times on blocked cache.Geoffrey Blake
2011-05-23O3: Fix issue with interrupts/faults occuring in the middle of a macro-opGeoffrey Blake
2011-05-21garnet: use vnet_type from protocol to decide buffer depthsTushar Krishna
2011-05-20slicc: added vnet_type to MI_exampleTushar Krishna
2011-05-18gcc: fix an uninitialized variable warning from G++ 4.5Nathan Binkert
2011-05-18slicc: added vnet_type field to identify response vnets from othersTushar Krishna
2011-05-18garnet: rename and rearrange config parameters.Tushar Krishna
2011-05-13ARM: Generate condition code setting code based on which codes are set.Ali Saidi
2011-05-13ARM: Construct the predicate test register for more instruction programatically.Ali Saidi
2011-05-13ARM: Further break up condition code into NZ, C, V bits.Ali Saidi
2011-05-13ARM: Remove the saturating (Q) condition code from the renamed register.Ali Saidi
2011-05-13ARM: Break up condition codes into normal flags, saturation, and simd.Ali Saidi
2011-05-13Trace: Allow printing ASIDs and selectively tracing based on user/kernel code.Chander Sudanthi
2011-05-13ARM: Better RealView/Versatile EB platform support.Chander Sudanthi
2011-05-13O3: Fix an issue with a load & branch instruction and mem dep squashingGeoffrey Blake
2011-05-12stats: delete mysql supportNathan Binkert
2011-05-12stats: move code that loops over all stats into pythonNathan Binkert
2011-05-12stats: better expose statistics to python.Nathan Binkert
2011-05-09work around gcc 4.5 warningNathan Binkert
2011-05-07NetworkTest: added sim_cycles parameter to the network tester.Tushar Krishna
2011-05-07network: added Torus and Pt2Pt topologiesTushar Krishna
2011-05-07Trace: Remove the options trace-help and trace-flagsNilay Vaish
2011-05-06X86: Fix the Lldt instructions so they load the ldtr and not the tr.Gabe Black
2011-05-05ruby: use RubyMemory flag & remove setDebug() functionalityKorey Sewell
2011-05-04ARM: Add support for loading the a bootloader and configuring parameters for itAli Saidi
2011-05-04ARM: Implement WFE/WFI/SEV semantics.Prakash Ramrakhyani
2011-05-04ARM: Add support for MP misc regs and broadcast flushes.Ali Saidi
2011-05-04ARM: Make GIC handle IPIs and multiple processors.Prakash Ramrakhyani
2011-05-04ARM: Add snoop control unit device.Ali Saidi
2011-05-04ARM: Add support for some more registers in the real view controller.Ali Saidi
2011-05-04Debug: Add a function to cause the simulator to create a checkpoint from GDB.Ali Saidi
2011-05-04CPU: Add some useful debug message to the timing simple cpu.Ali Saidi
2011-05-04CPU: Fix a case where timing simple cpu faults can nest.Ali Saidi
2011-05-04O3: Remove assertion for case that is actually handled in code.Ali Saidi