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2011-03-31Ruby: Add new object called WireBuffer to mimic a Wire.Lisa Hsu
This is a substitute for MessageBuffers between controllers where you don't want messages to actually go through the Network, because requests/responses can always get reordered wrt to one another (even if you turn off Randomization and turn on Ordered) because you are, after all, going through a network with contention. For systems where you model multiple controllers that are very tightly coupled and do not actually go through a network, it is a pain to have to write a coherence protocol to account for mixed up request/response orderings despite the fact that it's completely unrealistic. This is *not* meant as a substitute for real MessageBuffers when messages do in fact go over a network.
2011-03-31Ruby: have the rubytester pass contextId to Ruby.Lisa Hsu
2011-03-31Ruby: enable multiple sequencers in one controller.Lisa Hsu
2011-03-31Ruby: pass Packet->Req->contextId() to Ruby.Lisa Hsu
It is useful for Ruby to understand from whence request packets came. This has all request packets going into Ruby pass the contextId value, if it exists. This supplants the old libruby proc_id value passed around in all the Messages, so I've also removed the unused unsigned proc_id; member generated by SLICC for all Message types.
2011-03-31Ruby: Bug in SLICC forgot semicolon at end of code.Lisa Hsu
2011-03-29sim: typecast Tick to UTick for eventQ assertKorey Sewell
2011-03-29Power: Fix compilation.Gabe Black
2011-03-28This patch supports cache flushing in MOESI_hammerSomayeh Sardashti
2011-03-26mips: cleanup ISA-specific codeKorey Sewell
*** (1): get rid of expandForMT function MIPS is the only ISA that cares about having a piece of ISA state integrate multiple threads so add constants for MIPS and relieve the other ISAs from having to define this. Also, InOrder was the only core that was actively calling this function * * * (2): get rid of corespecific type The CoreSpecific type was used as a proxy to pass in HW specific params to a MIPS CPU, but since MIPS FS hasnt been touched for awhile, it makes sense to not force every other ISA to use CoreSpecific as well use a special reset function to set it. That probably should go in a PowerOn reset fault anyway.
2011-03-25Arm: Add in a missing miscRegName.Gabe Black
2011-03-24Arm: Get rid of unused and incomplete setCp15Register and readCp15Register.Gabe Black
2011-03-24Arm: Get rid of the unused copyStringArray32 method from Arm process classes.Gabe Black
2011-03-24ISA parser: Set up op_src_decl and op_dest_decl for pc operands.Gabe Black
2011-03-22This patch fixes a build error in networktest.cc that occurs with gcc4.2Tushar Krishna
2011-03-22Ruby: Remove CacheMsg class from SLICCNilay Vaish
The goal of the patch is to do away with the CacheMsg class currently in use in coherence protocols. In place of CacheMsg, the RubyRequest class will used. This class is already present in slicc_interface/RubyRequest.hh. In fact, objects of class CacheMsg are generated by copying values from a RubyRequest object.
2011-03-21This patch makes garnet use the info about active and inactive vnets during ↵Tushar Krishna
allocation and power estimations etc
2011-03-21fix garnet fleible pipelineTushar Krishna
2011-03-21This patch adds the network tester for simple and garnet networks.Tushar Krishna
The tester code is in testers/networktest. The tester can be invoked by configs/example/ruby_network_test.py. A dummy coherence protocol called Network_test is also addded for network-only simulations and testing. The protocol takes in messages from the tester and just pushes them into the network in the appropriate vnet, without storing any state.
2011-03-20SLICC: Remove WakeUp* import calls from ast/__init__.pyNilay Vaish
I had recently committed a patch that removed the WakeUp*.py files from the slicc/ast directory. I had forgotten to remove the import calls for these files from slicc/ast/__init__.py. This resulted in error while running regressions on zizzer. This patch does the needful.
2011-03-19Ruby: Convert CacheRequestType to RubyRequestTypeNilay Vaish
This patch converts CacheRequestType to RubyRequestType so that both the protocol dependent and independent code makes use of the same request type.
2011-03-19Ruby: Convert AccessModeType to RubyAccessModeNilay Vaish
This patch converts AccessModeType to RubyAccessMode so that both the protocol dependent and independent code uses the same access mode.
2011-03-19MOESI_hammer: minor fixes to full-bit dirBrad Beckmann
2011-03-19Ruby: dma retry fixBrad Beckmann
This patch fixes the problem where Ruby would fail to call sendRetry on ports after it nacked the port. This patch is particularly helpful for bursty dma requests which often include several packets.
2011-03-19RubyPort: minor fixes to trace flag and dprintfsBrad Beckmann
2011-03-19ruby: added useful dma progress dprintfBrad Beckmann
2011-03-19slicc: improved invalid transition messageBrad Beckmann
2011-03-19MOESI_hammer: fixed dma bug with shared dataBrad Beckmann
2011-03-19MOESI_CMP_directory: significant dma bug fixesBrad Beckmann
2011-03-18SLICC: Remove external_type for structuresNilay Vaish
In SLICC, in order to define a type a data type for which it should not generate any code, the keyword external_type is used. For those data types for which code should be generated, the keyword structure is used. This patch eliminates the use of keyword external_type for defining structures. structure key word can now have an optional attribute external, which would be used for figuring out whether or not to generate the code for this structure. Also, now structures can have functions as well data members in them.
2011-03-18SLICC: Remove the keyword wake_up_dependentsNilay Vaish
In order to add stall and wait facility for protocols, a keyword wake_up_dependents was introduced. This patch removes the keyword, instead this functionality is now implemented as function call.
2011-03-18SLICC: Remove the keyword wake_up_all_dependentsNilay Vaish
In order to add stall and wait facility for protocols, a keyword wake_up_all_dependents was introduced. This patch removes the keyword, instead this functionality is now implemented as function call.
2011-03-18swig: get rid of m5.internal.random module (swig/random.i)Steve Reinhardt
Thanks to swig this was interfering with the standard Python random module. The only function in that module was seed(), which erroneously called srand48(). Moved the function to m5.internal.core, renamed it seedRandom(), and made it call random_mt.init() instead.
2011-03-18base: disable FastAlloc in debug builds by defaultSteve Reinhardt
FastAlloc's reuse policies can mask allocation bugs, so we typically want it disabled when debugging. Set FORCE_FAST_ALLOC to enable even when debugging, and set NO_FAST_ALLOC to disable even in non-debug builds.
2011-03-17Automated merge with ssh://hg@repo.m5sim.org/m5Ali Saidi
2011-03-17ARM: Add minimal ARM_SE support for m5threads.Chris Emmons
Updated some of the assembly code sequences to use armv7 instructions and coprocessor 15 for storing the TLS pointer.
2011-03-17ARM: Fix subtle bug in LDM.Ali Saidi
If the instruction faults mid-op the base register shouldn't be written back.
2011-03-17ARM: Implement the Instruction Set Attribute Registers (ISAR).Ali Saidi
The ISAR registers describe which features the processor supports. Transcribe the values listed in section B5.2.5 of the ARM ARM into the registers as read-only values
2011-03-17ARM: Identify branches as conditional or unconditional and direct or indirect.Ali Saidi
2011-03-17ARM: Fix small bug with VLDM/VSTM instructions.Ali Saidi
2011-03-17ARM: Detect and skip udelay() functions in linux kernel.Ali Saidi
This change speeds up booting, especially in MP cases, by not executing udelay() on the core but instead skipping ahead tha amount of time that is being delayed.
2011-03-17ARM: Allow conditional quiesce instructions.Ali Saidi
This patch prevents not executed conditional instructions marked as IsQuiesce from stalling the pipeline indefinitely. If the instruction is not executed the quiesceSkip psuedoinst is called which schedules a wakes up call to the fetch stage.
2011-03-17ARM: Fix RFE macrop.Matt Horsnell
This changes the RFE macroop into 3 microops: URa = [sp]; URb = [sp+4]; // load CPSR,PC values from stack sp = sp + offset; // optionally auto-increment PC = URa; CPSR = URb; // write to the PC and CPSR. Importantly: - writing to PC is handled in the last micro-op. - loading occurs prior to state changes.
2011-03-17ARM: Rename registers used as temporary state by microops.Matt Horsnell
2011-03-17O3: Send instruction back to fetch on squash to seed predecoder correctly.Ali Saidi
2011-03-17O3: Cleanup the commitInfo comm struct.Ali Saidi
Get rid of unused members and use base types rather than derrived values where possible to limit amount of state.
2011-03-17ARM: Previous change didn't end up setting instFlags, this does.Ali Saidi
2011-03-17Mem: Fix issue with dirty block being lost when entire block transferred to ↵Ali Saidi
non-cache. This change fixes the problem for all the cases we actively use. If you want to try more creative I/O device attachments (E.g. sharing an L2), this won't work. You would need another level of caching between the I/O device and the cache (which you actually need anyway with our current code to make sure writes propagate). This is required so that you can mark the cache in between as top level and it won't try to send ownership of a block to the I/O device. Asserts have been added that should catch any issues.
2011-03-17O3: Fix unaligned stores when cache blockedAli Saidi
Without this change the a store can be issued to the cache multiple times. If this case occurs when the l1 cache is out of mshrs (and thus blocked) the processor will never make forward progress because each cycle it will send a single request using the recently freed mshr and not completing the multipart store. This will continue forever.
2011-03-17Ruby: minor bugfix, line did not adhere to some macro usage conventions.Lisa Hsu
2011-03-17Ruby: expose a simple mod function in slicc interface.Lisa Hsu