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2014-01-24cpu: Add support for Memory+Barrier instruction types in O3 cpu.Giacomo Gabrielli
2014-01-24cpu: Add support for instructions that zero cache lines.Ali Saidi
2014-01-24cpu: Add CPU support for generatig wake up events when LLSC adresses are ↵Ali Saidi
snooped. This patch add support for generating wake-up events in the CPU when an address that is currently in the exclusive state is hit by a snoop. This mechanism is required for ARMv8 multi-processor support.
2014-01-24mem: Add flag to request if it was generated by a page table walkGiacomo Gabrielli
2014-01-24mem: Add support for a security bit in the memory systemGiacomo Gabrielli
This patch adds the basic building blocks required to support e.g. ARM TrustZone by discerning secure and non-secure memory accesses.
2014-01-24sim: Add openat/fstatat syscalls and fix mremapChris Adeniyi-Jones
This patch adds support for the openat and fstatat syscalls and broadens the support for mremap to make it work on OS X.
2014-01-24mem: Remove explict cast from memhelper.Ali Saidi
Previously we were casting the result type to the the memory type which is incorrect for things like dual-memory operations which still return a single result.
2014-01-24Cache: Collect very basic stats on tag and data accessesTimothy M. Jones
Adds very basic statistics on the number of tag and data accesses within the cache, which is important for power modelling. For the tags, simply count the associativity of the cache each time. For the data, this depends on whether tags and data are accessed sequentially, which is given by a new parameter. In the parallel case, all data blocks are accessed each time, but with sequential accesses, a single data block is accessed only on a hit.
2014-01-24mem: per-thread cache occupancy and per-block agesDam Sunwoo
This patch enables tracking of cache occupancy per thread along with ages (in buckets) per cache blocks. Cache occupancy stats are recalculated on each stat dump.
2014-01-24base: add support for probe points and common probesMatt Horsnell
The probe patch is motivated by the desire to move analytical and trace code away from functional code. This is achieved by the probe interface which is essentially a glorified observer model. What this means to users: * add a probe point and a "notify" call at the source of an "event" * add an isolated module, that is being used to carry out *your* analysis (e.g. generate a trace) * register that module as a probe listener Note: an example is given for reference in src/cpu/o3/simple_trace.[hh|cc] and src/cpu/SimpleTrace.py What is happening under the hood: * every SimObject maintains has a ProbeManager. * during initialization (src/python/m5/simulate.py) first regProbePoints and the regProbeListeners is called on each SimObject. this hooks up the probe point notify calls with the listeners. FAQs: Why did you develop probe points: * to remove trace, stats gathering, analytical code out of the functional code. * the belief that probes could be generically useful. What is a probe point: * a probe point is used to notify upon a given event (e.g. cpu commits an instruction) What is a probe listener: * a class that handles whatever the user wishes to do when they are notified about an event. What can be passed on notify: * probe points are templates, and so the user can generate probes that pass any type of argument (by const reference) to a listener. What relationships can be generated (1:1, 1:N, N:M etc): * there isn't a restriction. You can hook probe points and listeners up in a 1:1, 1:N, N:M relationship. They become useful when a number of modules listen to the same probe points. The idea being that you can add a small number of probes into the source code and develop a larger number of useful analysis modules that use information passed by the probes. Can you give examples: * adding a probe point to the cpu's commit method allows you to build a trace module (outputting assembler), you could re-use this to gather instruction distribution (arithmetic, load/store, conditional, control flow) stats. Why is the probe interface currently restricted to passing a const reference: * the desire, initially at least, is to allow an interface to observe functionality, but not to change functionality. * of course this can be subverted by const-casting. What is the performance impact of adding probes: * when nothing is actively listening to the probes they should have a relatively minor impact. Profiling has suggested even with a large number of probes (60) the impact of them (when not active) is very minimal (<1%).
2014-01-24sim: Expose the current voltage for each object as a statAndreas Hansson
2014-01-24sim: Expose the current clock period as a statAndreas Hansson
This patch adds observability to the clock period of the clock domains by including it as a stat. As a result of adding this, the regressions will be updated in a separate patch.
2014-01-24mem: track per-request latencies and access depths in the cache hierarchyMatt Horsnell
Add some values and methods to the request object to track the translation and access latency for a request and which level of the cache hierarchy responded to the request.
2014-01-24config: Make the Clock a Tick parameter like Latency/FrequencyAndreas Hansson
This patch makes the Clock a TickParamValue just like Latency/Frequency. There is no longer any need to distinguish it (originally needed to support multiplication).
2014-01-24x86: Fix memory leak in table walkerAndreas Hansson
This patch fixes a memory leak in the table walker, by ensuring that the sender state is deleted again if the request packet cannot be successfully sent.
2014-01-24cpu: Relax check on squashed non-speculative instructionsAndreas Hansson
This patch relaxes the check performed when squashing non-speculative instructions, as it caused problems with loads that were marked ready, and then stalled on a blocked cache. The assertion is now allowing memory references to be non-faulting.
2014-01-24cpu: remove faulty simpoint basic block inst count assertionDam Sunwoo
This patch removes an assertion in the simpoint profiling code that asserts that a previously-seen basic block has the exact same number of instructions executed as before. This can be false if the basic block generates aborts or takes interrupts at different locations within the basic block. The basic block profiling are not affected significantly as these events are rare in general.
2014-01-17ruby: remove unused label no_vectorNilay Vaish
2014-01-10ruby: move all statistics to stats.txt, eliminate ruby.statsNilay Vaish
2014-01-10stats: add function for adding two histogramsNilay Vaish
This patch adds a function to the HistStor class for adding two histograms. This functionality is required for Ruby. It also adds support for printing histograms in a single line.
2014-01-09ruby: fix bug introduced to revision 8523754f8885Nilay Vaish
2014-01-08ruby: slicc: remove variable 'addr' used in calls to doTransitionNilay Vaish
This variable causes trouble if a variable of same name is declared in a protocol file. Hence it is being eliminated.
2014-01-04ruby: add a three level MESI protocol.Nilay Vaish
The first two levels (L0, L1) are private to the core, the third level (L2)is possibly shared. The protocol supports clustered designs. For example, one can have two sets of two cores. Each core has an L0 and L1 cache. There are two L2 controllers where each set accesses only one of the L2 controllers.
2014-01-04ruby: rename MESI_CMP_directory to MESI_Two_LevelNilay Vaish
This is because the next patch introduces a three level hierarchy. --HG-- rename : build_opts/ALPHA_MESI_CMP_directory => build_opts/ALPHA_MESI_Two_Level rename : build_opts/X86_MESI_CMP_directory => build_opts/X86_MESI_Two_Level rename : configs/ruby/MESI_CMP_directory.py => configs/ruby/MESI_Two_Level.py rename : src/mem/protocol/MESI_CMP_directory-L1cache.sm => src/mem/protocol/MESI_Two_Level-L1cache.sm rename : src/mem/protocol/MESI_CMP_directory-L2cache.sm => src/mem/protocol/MESI_Two_Level-L2cache.sm rename : src/mem/protocol/MESI_CMP_directory-dir.sm => src/mem/protocol/MESI_Two_Level-dir.sm rename : src/mem/protocol/MESI_CMP_directory-dma.sm => src/mem/protocol/MESI_Two_Level-dma.sm rename : src/mem/protocol/MESI_CMP_directory-msg.sm => src/mem/protocol/MESI_Two_Level-msg.sm rename : src/mem/protocol/MESI_CMP_directory.slicc => src/mem/protocol/MESI_Two_Level.slicc rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/ruby.stats rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simerr rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simout rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/system.pc.com_1.terminal rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/ruby.stats rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/ruby.stats rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/ruby.stats rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simout rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/ruby.stats rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt
2014-01-04ruby: add support for clustersNilay Vaish
A cluster over here means a set of controllers that can be accessed only by a certain set of cores. For example, consider a two level hierarchy. Assume there are 4 L1 controllers (private) and 2 L2 controllers. We can have two different hierarchies here: a. the address space is partitioned between the two L2 controllers. Each L1 controller accesses both the L2 controllers. In this case, each L1 controller is a cluster initself. b. both the L2 controllers can cache any address. An L1 controller has access to only one of the L2 controllers. In this case, each L2 controller along with the L1 controllers that access it, form a cluster. This patch allows for each controller to have a cluster ID, which is 0 by default. By setting the cluster ID properly, one can instantiate hierarchies with clusters. Note that the coherence protocol might have to be changed as well.
2014-01-04ruby: some small changesNilay Vaish
2014-01-03python: provide better error message for wrapped C++ methodsSteve Reinhardt
If you successfully export a C++ SimObject method, but try to invoke it from Python before the C++ object is created, you get a confusing error that says the attribute does not exist, making you question whether you successfully exported the method at all. In reality, your only problem is that you're calling the method too soon. This patch enhances the error message to give you a better clue.
2014-01-03python: don't die on assignment to cloned objectSteve Reinhardt
Updating the SimObject topology of a cloned hierarchy is a little dangerous, in that cloning is a "deep copy" and the clone does not inherit SimObject updates the same way it would inherit scalar variable assignments. However, because of various SimObject-valued proxy parameters, like 'memories', 'clk_domain', and 'system', it turns out that there are a number of implicit topology changes that happen at instantiation, which means that these changes are impossible to avoid. So in order to make cloning systems useful, this error has to go. Changing it to a warning produces a lot of noise, so it seems best just to delete it.
2013-12-29sim: Add support for dynamic frequency scalingChristopher Torng
This patch provides support for DFS by having ClockedObjects register themselves with their clock domain at construction time in a member list. Using this list, a clock domain can update each member's tick to the curTick() before modifying the clock period. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-12-29mips: Floating point convert bug fixChristopher Torng
In mips architecture, floating point convert instructions use the FloatConvertOp format defined in src/arch/mips/isa/formats/fp.isa. The type of the operands in the ISA description file (_sw for signed word, or _sf for signed float, etc.) is used to create a type for the operand in C++. Then the operand is converted using the fpConvert() function in src/arch/mips/utility.cc. If we are converting from a word to a float, and we want to convert 0xffffffff, we expect -1 to be passed into fpConvert(). Instead, we see MAX_INT passed in. Then fpConvert() converts _val_ to MAX_INT in single-precision floating point, and we get the wrong value. To fix it, the signs of the convert operands are being changed from unsigned to signed in the MIPS ISA description. Then, the FloatConvertOp format is being changed to insert a int32_t into the C++ code instead of a uint32_t. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-12-26ruby: fix bugs in mesi cmp directory protocolNilay Vaish
This patch fixes couple of bugs in the L2 controller of the mesi cmp directory protocol. 1. The state MT_I was transitioning to NP on receiving a clean writeback from the L1 controller. This patch makes it inform the directory controller about the writeback. 2. The L2 controller was sending the dirty bit to the L1 controller and the L2 controller used writeback from the L1 controller to update the dirty bit unconditionally. Now, the L1 controller always assumes that the incoming data is clean. The L2 controller updates the dirty bit only when the L1 controller writes to the block. 3. Certain unused functions and events are being removed.
2013-12-20ruby: slicc: replace max_in_port_rank with number of inportsNilay Vaish
This patch replaces max_in_port_rank with the number of inports. The use of max_in_port_rank was causing spurious re-builds and incorrect initialization of variables in ruby related regression tests. This was due to the variable value being used across threads while compiling when it was not meant to be. Since the number of inports is state machine specific value, this problem should get solved.
2013-12-20ruby: declare variables to be unsigned in Address.hhNilay Vaish
2013-12-20ruby: mesi: remove owner and sharer fields from directory tagsNilay Vaish
The directory controller should not have the sharer field since there is only one level 2 cache. Anyway the field was not in use. The owner field was being used to track the l2 cache version (in case of distributed l2) that has the cache block under consideration. The information is not required since the version of the level 2 cache can be obtained from a subset of the address bits.
2013-12-03sim: reset stats after startupNilay Vaish
Currently statistics are reset after the initial / checkpoint state has been loaded. But ruby does some checkpoint processing in its startup() function. So the stats need to be reset after the startup() function has been called. This patch moves the class to stats.reset() to achieve this change in functionality.
2013-12-03cpu: call BaseCPU startup() function in o3 cpuNilay Vaish
2013-11-29base: Fix race in PollQueue and remove SIGALRM workaroundAndreas Sandberg
There is a race between enabling asynchronous IO for a file descriptor and IO events happening on that descriptor. A SIGIO won't normally be delivered if an event is pending when asynchronous IO is enabled. Instead, the signal will be raised the next time there is an event on the FD. This changeset simulates a SIGIO by setting the async_io flag when setting up asynchronous IO for an FD. This causes the main event loop to poll all file descriptors to check for pending IO. As a consequence of this, the old SIGALRM hack should no longer be needed and is therefore removed.
2013-11-29base: Clean up signal handlingAndreas Sandberg
The PollEvent class dynamically installs a SIGIO and SIGALRM handler when a file handler is registered. Most signal handlers currently get registered in the initSignals() function. This changeset moves the SIGIO/SIGALRM handlers to initSignals() to live with the other signal handlers. The original code installs SIGIO and SIGALRM with the SA_RESTART option to prevent syscalls from returning EINTR. This changeset consistently uses this flag for all signal handlers to ensure that other signals that trigger asynchronous behavior (e.g., statistics dumping) do not cause undesirable EINTR returns.
2013-11-26sim: correct ticksToCycles() function.Nilay Vaish
2013-10-15kvm: Set the perf exclude_host attribute if availableAndreas Sandberg
The performance counting framework in Linux 3.2 and onwards supports an attribute to exclude events generated by the host when running KVM. Setting this attribute allows us to get more reliable measurements of the guest machine. For example, on a highly loaded system, the instruction counts from the guest can be severely distorted by the host kernel (e.g., by page fault handlers). This changeset introduces a check for the attribute and enables it in the KVM CPU if present.
2013-11-26x86: Implementation of Int3 and Int_Ib in long modeChristian Menard
This is an implementation of the x86 int3 and int immediate instructions for long mode according to 'AMD64 Programmers Manual Volume 3'.
2013-11-26kvm: Remove the unused hostFreq member from BaseKvmCPUAndreas Sandberg
2013-11-25sim: simulate with multiple threads and event queuesSteve Reinhardt ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E%2C%20Ali%20Saidi%20%3CAli.Saidi%40ARM.com%3E)
This patch adds support for simulating with multiple threads, each of which operates on an event queue. Each sim object specifies which eventq is would like to be on. A custom barrier implementation is being added using which eventqs synchronize. The patch was tested in two different configurations: 1. ruby_network_test.py: in this simulation L1 cache controllers receive requests from the cpu. The requests are replied to immediately without any communication taking place with any other level. 2. twosys-tsunami-simple-atomic: this configuration simulates a client-server system which are connected by an ethernet link. We still lack the ability to communicate using message buffers or ports. But other things like simulation start and end, synchronizing after every quantum are working. Committed by: Nilay Vaish
2013-11-15cpu: allow the fetch buffer to be smaller than a cache lineAnthony Gutierrez
the current implementation of the fetch buffer in the o3 cpu is only allowed to be the size of a cache line. some architectures, e.g., ARM, have fetch buffers smaller than a cache line, see slide 22 at: http://www.arm.com/files/pdf/at-exploring_the_design_of_the_cortex-a15.pdf this patch allows the fetch buffer to be set to values smaller than a cache line.
2013-11-15cpu: Fix Checker register index useAndreas Hansson
This patch fixes an issue in the checker CPU register indexing. The code will not even compile using LTO as deep inlining causes the used index to be outside the array bounds.
2013-11-14tests: suppress output on switcheroo testsSteve Reinhardt
The output from the switcheroo tests is voluminous and (because it includes timestamps) highly sensitive to minor changes, leading to extremely large updates to the reference outputs. This patch addresses this problem by suppressing output from the tests. An internal parameter can be set to enable the output. Wiring that up to a command-line flag (perhaps even the rudimantary -v/-q options in m5/main.py) is left for future work.
2013-11-12sim: fix event priority name for debug-start optionAnthony Gutierrez
2013-11-01mem: Fixes for DRAM stats accountingAndreas Hansson
This patch fixes a number of stats accounting issues in the DRAM controller. Most importantly, it separates the system interface and DRAM interface so that it is clearer what the actual DRAM bandwidth (and consequently utilisation) is.
2013-11-01mem: Fix the LPDDR3 page sizeAndreas Hansson
This patch corrects the LPDDR3 page size, which was set too low.
2013-11-01mem: Adding stats for DRAM power calculationNeha Agarwal
This patch adds stats which are used for offline power calculation from the 'Micron Power Calculator' spreadsheet.