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If set, the granularity bit indicates that the segment limit of segment
descriptors shall be interpreted as number of 4K blocks rather than
bytes.
The high part (bit 48 to 51) of segment descriptor limits is only 4 bits
wide while the low part (bit 0 to 15) spans 16 bits.
Change-Id: Ie386224ca815275fdb31498fe68310ed9c62cc87
Reviewed-on: https://gem5-review.googlesource.com/7601
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
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This makes riscv compile with the version of clang(++) I have on my
workstation.
Change-Id: I0478616810fbc8a715fd61323b7e0f73676c8328
Reviewed-on: https://gem5-review.googlesource.com/7643
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
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The cprintf functions don't know ahead of time what format characters
are going to be used with what underlying data types, and so any
type must be minimally usable with the default specialization of
format_integer, format_char, format_float and format_string. All of
those functions ultimately print their parameter with out << data
except the one which prints stringstreams. That function accesses the
buffer of the string stream with .str(), and then prints that instead.
That should technically work out ok as long as stringstreams are only
printed using %s, but there's no way to guarantee that ahead of time.
To avoid that problem, and because gem5 doesn't ever actually use the
ability to print stringstreams directly, this change removes that
feature and modifies the corresponding part of the unit test.
If we ever do want to print the contents of a string stream, it won't
be difficult to add a .str() to it.
Change-Id: Id902eaff042b96b374efe0183e5e3be9626e8c88
Reviewed-on: https://gem5-review.googlesource.com/7642
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
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If they're needed, they'd be fairly easy to recreate and are also
available in the revision history.
Change-Id: I5cf5e4b1271ce488016464048de69bc643dee4d9
Reviewed-on: https://gem5-review.googlesource.com/7641
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
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Move massive initialization routine to the bottom of miscregs.cc.
Additionally, share register metadata across ISA instances by
making lookUpMiscReg a static member of the ISA and only
initializing it once.
Change-Id: I6d6ab26200c4e781151cc6efd97ce2420e2bf4cc
Signed-off-by: Curtis Dunham <Curtis.Dunham@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6803
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Implement proper handling of RES0/RES1 and RAZ/RAO bitfields.
Change-Id: I344c32c3fb1d142acfb0521ba3590ddd2b1f5360
Signed-off-by: Curtis Dunham <Curtis.Dunham@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6802
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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The mappings for sharing a backing store between AArch32
and AArch64 system registers are made clearer using an
initializer object.
Change-Id: I29dcfab2797b4d36b3182342997edffde334a291
Signed-off-by: Curtis Dunham <Curtis.Dunham@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6801
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Enables automatic generation of Device Trees for RealView PCI host
controllers. Note that some parts are more hard coded than you'd want,
but this is due to the limited understanding the PCI host has of its
configuration (i.e. it doesn't know all memory ranges). Fixing this,
for now at least, went beyond the scope and intentions of the
Device Tree generating code: use with care!
Change-Id: I2041871e0eb4d04fb5191257c47dd38649d1c0cc
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5967
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Adds Device Tree methods for the energy controller to allow for
DVFS simulations with automatically generated DTB files
Change-Id: Id8682f07dff1bbe63987e757faa0694e03ee86ab
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5966
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Implements the Device Tree generating code for devices required by the
RealView VExpress_GEM5_V1 platform
Change-Id: I14244b2f3c028cbddba3c23ce7433fe3b301a0e8
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5965
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Implements a high level method for generating a Device Tree node for
an AbstractMemory object.
Change-Id: I544ec642f182f103df26de535fdfaf03b3787a08
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5964
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Equips cpu models with a method to generate the cpu node.
Note: even though official documentation requires that CPU ids start
counting from 0 in every cluster, GEM5 requires a globally unique cpu_id.
Change-Id: Ida3e17af3124a68ef7dbf2449cd034dfc3ec39df
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5963
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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This patch adds an extra layer to the pyfdt library such that usage
gets easier and device tree nodes can be specified in less code,
without limiting original usage. Note to not import both the pyfdt
and fdthelper in the same namespace (but generally fdthelper is all
you need, because it supplies the same classes even when they are not
extended in any way)
Also, this patch lays out the primary functionality for generating a
device tree, where every SimObject gets an empty generateDeviceTree
method and ArmSystems loop over their children in an effort to merge
all the nodes. Devices are implemented in other patches.
Change-Id: I4d0a0666827287fe42e18447f19acab4dc80cc49
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5962
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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This patch adds pyfdt.py to the m5.ext module. This is used in
succeeding patches for generating and editing dtb files and flat
device trees for DT autogeneration.
The file is in the m5_root/src/python/m5/ext directory, as opposed to
the m5_root/ext, because this library is part of the m5 object space
and linking to the m5_root/ext directory from the SConscript file
in src/python can not be done reliably. Linking from the root level
SConscript is also not an option, because it doesn't have the PySource
method defined.
Cloned from: https://github.com/superna9999/pyfdt
Commit: accbcd254584c9295a18878d32999d0c7c156f8e
Version: 0.3
Change-Id: I928bdc912a9507d1f8a3290acf445c7cae496552
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5961
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Within a device tree, the GenericTimer device needs to point (via phandle)
to a clock domain which is itself also an object in the device tree. Within
gem5, clock domains are managed by making all clocked SimObjects inherit
from ClockedObject rather than SimObject.
Without this change, the GenericTimer is unable to generate the appropriate
clock domain phandle, and will crash during DTB autogeneration.
Change-Id: I6d3fb6362847c6a01720b2f14b3d595d1e59f01f
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4960
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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clang reports an error otherwise and fails to compile.
Change-Id: I3603d6c710641f1289e35c67f89a49f5cb71e95e
Reviewed-on: https://gem5-review.googlesource.com/7582
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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clang was getting very upset and interpretting a member function
pointer as a call to the actual underlying function, and then
complaining that it was a non-static function call without an instance.
It seems what it was really upset about was that the class who's scope
the member function pointer belonged to (the current class) wasn't done
being defined. This *should* be ok as far as I can tell, but clang was
having none of it.
This change reworks how the type of the setter function arguments are
determined to work around that limitation. The bitunion test was run
with clang++ and g++ and both pass, and I've built gem5.opt for ARM
successfully.
Change-Id: Ib9351784a897af4867fe08045577e0247334ea11
Reviewed-on: https://gem5-review.googlesource.com/7581
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
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This patch adds support for cache flushing instructions in x86.
It piggybacks on support for similar instructions in arm ISA
added by Nikos Nikoleris. I have tested each instruction using
microbenchmarks.
Change-Id: I72b6b8dc30c236a21eff7958fa231f0663532d7d
Reviewed-on: https://gem5-review.googlesource.com/7401
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
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This header is no longer used.
Change-Id: I8da7f8618d647dd11c581818c13855c4e20d32d2
Reviewed-on: https://gem5-review.googlesource.com/7351
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Rather than store the actual TLB entry that corresponds to a mapping,
we can just store some abstracted information (address, a few flags)
and then let the caller turn that into the appropriate entry. There
could potentially be some small amount of overhead from creating
entries vs. storing them and just installing them, but it's likely
pretty minimal since that only happens on a TLB miss (ideally rare),
and, if it is problematic, there could be some preallocated TLB
entries which are just minimally filled in as necessary.
This has the nice effect of finally making the page tables ISA
agnostic.
Change-Id: I11e630f60682f0a0029b0683eb8ff0135fbd4317
Reviewed-on: https://gem5-review.googlesource.com/7350
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
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The new version extracts all the x86 specific aspects of the class,
and builds the interface around a variable collection of template
arguments which are classes that represent the different levels of the
page table. The multilevel page table class is now much more ISA
independent.
Change-Id: Id42e168a78d0e70f80ab2438480cb6e00a3aa636
Reviewed-on: https://gem5-review.googlesource.com/7347
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
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Use the system object to allocate physical memory instead of manually
placing certain structures and then forcing the system to start other
allocations after them in physical memory.
Change-Id: Ie18c81645c3b648c64a6d7a649a0e50f7028f344
Reviewed-on: https://gem5-review.googlesource.com/7346
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
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Pass this constant into the page table constructor.
Change-Id: Icbf730f18d9dfcfebd10a196f7f799514728b0fb
Reviewed-on: https://gem5-review.googlesource.com/7345
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
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Don't get it from a global constant declared in an ISA header file.
Change-Id: Ie19440abdd76500a5e12e6791e6f755ad9e95af3
Reviewed-on: https://gem5-review.googlesource.com/7344
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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This avoids having a copy in the lookup function itself, and the
declaration of a lot of temporary TLB entry pointers in callers. The
gpu TLB seems to have had the most dependence on the original signature
of the lookup function, partially because it was relying on a somewhat
unsafe copy to a TLB entry using a base class pointer type.
Change-Id: I8b1cf494468163deee000002d243541657faf57f
Reviewed-on: https://gem5-review.googlesource.com/7343
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
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Since this type is now accessible through a clean interface, hide it
from anybody that tries to peak around the curtain.
Change-Id: I1257b6675a45b8648be459ad8e8d0f27a6feee6b
Reviewed-on: https://gem5-review.googlesource.com/7205
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
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The ARM types.hh file defined an STL style hash structure to operate
on the ExtMachInst, but it referred to the underlying storage type
using internal typedefs in the BitUnion types. To avoid having to do
that, this change adds a hash structure to bitunion.hh which will work
on any BitUnion, and gets rid of the ARM ExtMachInst version.
Change-Id: I7c1c84d61b59061fec98abaaeab6becd06537dee
Reviewed-on: https://gem5-review.googlesource.com/7204
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
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serialize.hh should not reference internal implementation details in
the underlying BitUnion types.
Change-Id: I1ce29243db63801b7788f037fdc54811bdab889c
Reviewed-on: https://gem5-review.googlesource.com/7203
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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Previously these relied on reaching into private internal definitions
in the BitUnion types.
Change-Id: Ia6c94de92986b85ec9e5fcb197459d450111fb36
Reviewed-on: https://gem5-review.googlesource.com/7202
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
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They are now oriented around a class which makes it easy to provide
custom setter/getter functions which let you set or read bits in an
arbitrary way.
Future additions may add the ability to add custom bitfield methods,
and index-able bitfields.
Change-Id: Ibd6d4d9e49107490f6dad30a4379a8c93bda9333
Reviewed-on: https://gem5-review.googlesource.com/7201
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
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Fold the GDBListener class into the main BaseRemoteGDB class, move
around a bunch of functions, convert a lot of internal functions to
be private, move some functions into the .cc, make some functions
non-virtual which didn't really need to be overridden.
Change-Id: Id0832b730b0fdfb2eababa5067e72c66de1c147d
Reviewed-on: https://gem5-review.googlesource.com/7422
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
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Now that Nothing inherits from PageTableBase directly, it can be
merged into FuncPageTable. This change also takes the opportunity to
rename the combined class to EmulationPageTable which lets you know
that it's specifically for SE mode.
Also remove the page table entry cache since it doesn't seem to
actually improve performance. The TLBs likely absorb the majority of
the locality, essentially acting like a cache like they would in real
hardware.
Change-Id: If1bcb91aed08686603bf7bee37298c0eee826e13
Reviewed-on: https://gem5-review.googlesource.com/7342
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
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KVM looks up translations using the image of the page table in the
guest's memory, but we don't have to. By maintaining that image in
addition to rather than instead of maintaining an abstract copy makes
our lookups faster, and ironically avoids duplicate implementation.
Change-Id: I9ff4cae6f7cf4027c3738b75f74eae50dde2fda1
Reviewed-on: https://gem5-review.googlesource.com/7341
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
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This patch applies correct miscellaneous or multiply-accumulate op
classes to floating point instructions which had previously been
incorrectly classed as add or multiply instructions.
Change-Id: I959dd8d3152aa341e0f060b003ce1da8c4d688fb
Reviewed-on: https://gem5-review.googlesource.com/6521
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
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Using the fetestexcept function to check for specific types of floating
point exceptions is unreliable for some kinds of
floating-point-to-integer conversion operations. RISC-V code used to
make use of them to check for some exceptional cases like overflow and
underflow, which caused incorrect output when compiler optimization is
turned on. This patch changes the use of fetestexcept to explicit checks
for those exceptional cases.
Change-Id: Id983906ea0664dc246e115a9e470d9ab7733bde1
Reviewed-on: https://gem5-review.googlesource.com/6402
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
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The code in this function was a little convoluted. This change attempts
to simplify it a little bit to make it easier to read.
Change-Id: I1ae557b9fede47fa89a9ea550bd0af8ad242449f
Reviewed-on: https://gem5-review.googlesource.com/7421
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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Using the architectural page table on x86 and the functional page table
on ARM, both with the twolf benchmark in SE mode, there was no
performance penalty for doing so, and again possibly a performance
improvement. By using a pointer instead of an inline instance, it's
possible for the actual type of the TLB entry to be hidden somewhat,
taking a step towards abstracting away another aspect of the ISAs.
Since the TLB entries are no longer overwritten and now need to be
allocated and freed, this change introduces return types from the
updateCache and eraseCacheEntry functions. These functions will return
the pointer to any entry which has been displaced from the cache which
the caller can either free or ignore, depending on whether the entry
has a purpose outside of the cache.
Because the functional page table stores its entries over a longer time
period, it will generally not delete the pointer returned from those
functions. The "architechtural" page table, ie the one which is backed
by memory, doesn't have any other use for the TlbEntrys and will delete
them. That leads to more news and deletes than there used to be.
To address that, and also to speed up the architectural page table in
general, it would be a good idea to augment the functional page table
with an image of the table in memory, instead of replacing it with one.
The functional page table would provide quick lookups and also avoid
having to translate page table entries to TLB entries, making
performance essentially equivalent to the functional case. The backing
page tables, which are primarily for consumption by the physical
hardware when in KVM, can be updated when mappings change but otherwise
left alone.
If we end up doing that, we could just let the ISA specific process
classes enable whatever additional TLB machinery they need, likely
a backing copy in memory, without any knowledge or involvement from
the ISA agnostic class. We would be able to get rid of the useArchPT
setting and the bits of code in the configs which set it.
Change-Id: I2e21945cd852bb1b3d0740fe6a4c5acbfd9548c5
Reviewed-on: https://gem5-review.googlesource.com/6983
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
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When switching an assert to a fatal while addressing recent review
feedback, I forgot to reverse the polarity of the condition, making
the fatal fire in exactly the opposite of the conditions it was meant
to.
Change-Id: Icf49864ef449052bbb0d427dca786006166575c4
Reviewed-on: https://gem5-review.googlesource.com/7381
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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Before this CL, the addTwoLevelCacheHierarchy() function uses the
default L2XBar class as the interconnect between CPU L1 caches and
L2. This CL allows passing a user-defined bus to overwrite the
default L2XBar by adding an optional argument to the function.
Change-Id: I917657272fd4924ee0bed882a226851afba26847
Reviewed-on: https://gem5-review.googlesource.com/7364
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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This patch fixes a potential crash if an unnamed CSR is accessed and
debug flags are enabled that print disassembly. Unknown CSRs will be
identified as "??" followed by the address that was used.
Change-Id: If5ac57f1422bd59c72a1a06206fa9d9dc05d21ef
Reviewed-on: https://gem5-review.googlesource.com/7321
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
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This changeset fixes a bug that was affecting the MOESI_CMP_token
protocol where setting the next timeout required an absolute tick in
the future.
Change-Id: Ibfdb59354e13c7e552cb3389e71bda010f333249
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7163
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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The function map_Address_to_DMA was used to route responses to the
first (and assumed to be the only) DMA engine in the system. This
function is now unused as protocols handle responses and route them to
the right DMA engine.
Change-Id: I2fba913cf2f12321d1a1e38e7ee85bdf26b8a47a
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7162
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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Previously the MESI_Two_Level protocol supported systems with a single
DMA engine and responses from the directory to DMA requests were
routed back to the only DMA engine. This changeset adds support for
multiple DMA engines in the system by routing the response to the DMA
engine that originally sent the request.
Change-Id: I10ceda682ea29746636862ec8ef2a9c4220ca045
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7161
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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This is instead of the architecture specific version.
Change-Id: I906ec16eee1f65f0e9b9c24b401430f9ea01637b
Reviewed-on: https://gem5-review.googlesource.com/7349
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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These were still inheriting from SimObject instead of BaseTLB, making
them incompatible with parameters which expect a BaseTLB.
Change-Id: I05115cc5515f745fdeb85e4dea8eded613647e40
Reviewed-on: https://gem5-review.googlesource.com/7348
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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This breaks one more architecture dependence outside of the ISAs.
Change-Id: I071f9ed73aef78e1cd1752247c183e30854b2d28
Reviewed-on: https://gem5-review.googlesource.com/6982
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
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This gets rid of an awkward NoArchPageTable class, and also gives the
arch a place to inject ISA specific parameters (specifically page size)
without having to have TheISA:: in the generic version of these types.
Change-Id: I1412f303460d5c43dafdb9b3cd07af81c908a441
Reviewed-on: https://gem5-review.googlesource.com/6981
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
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Several files in the repository were tracked with execute permissions
even though the files are just normal C/C++ files (and the one .isa).
Change-Id: I976b096acab4a1fc74c5699ef1f9b222c1e635c2
Reviewed-on: https://gem5-review.googlesource.com/7241
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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This patch makes use of ImmOp's polymorphism to remove unnecessary
casting from the implementations of arithmetic instructions with
immediate operands and to remove the CUIOp format by combining it with
the CIOp format (compressed arithmetic instructions with immediate
operands). Interestingly, RISC-V specifies that instructions with
unsigned immediate operands still need to sign-extend the immediates
from 12 (or 20) bits to 64 bits, so that is left alone.
Change-Id: If20d70c1e90f379b9ed8a4155b2b9222b6defe16
Reviewed-on: https://gem5-review.googlesource.com/6401
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Tuan Ta <qtt2@cornell.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
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This constant is, first, a #define, and second only used in one place.
In that one place, it appears that the code it guards is no longer
necessary in general. It was originally written to avoid refetching a
block of data that you're still in, even if you've moved slightly
farther in it because you're skipping the next instruction due to an
annulled branch delay slot. In reality however, in SPARC, the one ISA
I'm aware of which has this sort of branching behavior, the PC state
object will correctly determine that no branch is happening in these
cases. Code lower down in the loop will then recompute where fetching
should continue based on the next PC, automatically skipping the
annulled branch slot without misinterpretting the gap as a branch.
This change therefore also removes this block of code.
Change-Id: I820ebc9df10aeb4fcb69c12f6a784e9ec616743c
Reviewed-on: https://gem5-review.googlesource.com/6821
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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