| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2009-02-25 | X86: Implement a basic prefetch instruction. | Gabe Black | |
| 2009-02-25 | X86: Use the right portion of a register for stores. | Gabe Black | |
| 2009-02-25 | X86: Actually check page protections. | Gabe Black | |
| 2009-02-25 | X86: Update CS later so stack accesses have the right permission checks. | Gabe Black | |
| 2009-02-25 | CPU: Don't fetch when executing a macroop. | Gabe Black | |
| If the CPL changes mid macroop, the end of the instruction might not be priveleged enough to execute the beginning. | |||
| 2009-02-25 | X86: Use atCPL0 for accesses that are part of CPU machinery. | Gabe Black | |
| 2009-02-25 | X86: Add a flag to force memory accesses to happen at CPL 0. | Gabe Black | |
| 2009-02-25 | X86: Move where CS is set so CPL checks work out. | Gabe Black | |
| 2009-02-25 | X86: Implement inUserMode for x86. | Gabe Black | |
| 2009-02-25 | X86: Add a trace flag for tracing faults. | Gabe Black | |
| 2009-02-25 | X86: Implement the sysret instruction in long mode. | Gabe Black | |
| 2009-02-25 | X86: Implement the longmode versions of the syscall instruction. | Gabe Black | |
| 2009-02-25 | X86: Make the microcode assembler recognize r8-r15. | Gabe Black | |
| 2009-02-25 | X86: Add a wrattr microop. | Gabe Black | |
| 2009-02-25 | X86: Add a trace flag for the page table walker. | Gabe Black | |
| 2009-02-25 | X86: Make exceptions handle stack switching. | Gabe Black | |
| 2009-02-25 | X86: Implement the LTR instruction. | Gabe Black | |
| 2009-02-25 | X86: Fix segment limit checking. | Gabe Black | |
| 2009-02-25 | X86: Add a check to chks to verify a task state segment descriptor. | Gabe Black | |
| 2009-02-25 | X86: Add a check to chks which raises #GP(selector) if selector is NULL or ↵ | Gabe Black | |
| not in the GDT. | |||
| 2009-02-25 | X86: Add makeAtomicResponse to the read/write functions of x86 devices. | Gabe Black | |
| 2009-02-25 | X86: Fix the timing mode of the page table walker. | Gabe Black | |
| 2009-02-25 | X86: Make the X86 TLB take advantage of delayed translations, and get rid of ↵ | Gabe Black | |
| the fake TLB miss faults. | |||
| 2009-02-25 | CPU: Implement translateTiming which defers to translateAtomic, and convert ↵ | Gabe Black | |
| the timing simple CPU to use it. | |||
| 2009-02-25 | SPARC: Adjust a few instructions to not write registers in initiateAcc. | Gabe Black | |
| 2009-02-25 | X86: Make the stupd microop not update registers in initiateAcc. | Gabe Black | |
| 2009-02-25 | ISA: Replace the translate functions in the TLBs with translateAtomic. | Gabe Black | |
| 2009-02-25 | CPU: Get rid of translate... functions from various interface classes. | Gabe Black | |
| 2009-02-23 | stats: reorganize how parameters are stored and accessed. | Nathan Binkert | |
| 2009-02-23 | stats: move the limits stuff into the types.hh file | Nathan Binkert | |
| 2009-02-23 | stats: get rid of the convoluted 'database' code. | Nathan Binkert | |
| Just use the stuff directly and things ought to be more clear | |||
| 2009-02-23 | stats: Try to make the names of things more intuitive. | Nathan Binkert | |
| Basically, this means renaming several things called data to info, which is information about the statistics. Things that are named data now are actual data stored for the statistic. | |||
| 2009-02-23 | stats: clean up the statistics unittest | Nathan Binkert | |
| 2009-02-23 | stats: fix text printout for distributions | Nathan Binkert | |
| 2009-02-23 | stats: cleanup static stats to make startup work. | Nathan Binkert | |
| This is mainly to allow the unit test to run without requiring the standard M5 stats from being initialized (e.g. sim_seconds, sim_ticks, host_seconds) | |||
| 2009-02-23 | debug: Move debug_break into src/base | Nathan Binkert | |
| 2009-02-23 | X86: Pass whether an access was a read/write/fetch so faults can behave ↵ | Gabe Black | |
| accordingly. | |||
| 2009-02-20 | Remove unnecessary building of FreeList/RenameMap in InOrder. Clean-up ↵ | Korey Sewell | |
| comments and O3 extensions InOrder Thread Context | |||
| 2009-02-18 | events: Make trace events happen at the right priority. | Nathan Binkert | |
| Also, while we're at it, remember that priorities are in the Event class and add a disable method to disable tracing. | |||
| 2009-02-17 | Make etherdump timestamps zero-based. | Steve Reinhardt | |
| We previously used the actual wall time for the base timestamps, making etherdumps non-deterministic. This fixes that problem and gets rid of the "malformed packet" at the front that we needed to provide the right base timestamp to wireshark/tcpdump. | |||
| 2009-02-16 | sycalls: implement mremap() and add DATA flag for getrlimit(). mremap has ↵ | Lisa Hsu | |
| been tested on Alpha, compiles for the rest but not tested. I don't see why it wouldn't work though. | |||
| 2009-02-16 | Fixes to get prefetching working again. | Steve Reinhardt | |
| Apparently we broke it with the cache rewrite and never noticed. Thanks to Bao Yungang <baoyungang@gmail.com> for a significant part of these changes (and for inspiring me to work on the rest). Some other overdue cleanup on the prefetch code too. | |||
| 2009-02-15 | X86: Make the loader recognize 32 bit x86 processes. | Gabe Black | |
| 2009-02-15 | traceflags: fix --trace-help | Nathan Binkert | |
| 2009-02-10 | style | Nathan Binkert | |
| 2009-02-10 | Configs: Add support for the InOrder CPU model | Korey Sewell | |
| 2009-02-10 | InOrder: Import new inorder CPU model from MIPS. | Korey Sewell | |
| This model currently only works in MIPS_SE mode, so it will take some effort to clean it up and make it generally useful. Hopefully people are willing to help make that happen! | |||
| 2009-02-10 | syscall: Expose ioctl for MIPS | Korey Sewell | |
| 2009-02-10 | ExeTrace: Allow subclasses of the tracer to define their own prefix to dump | Korey Sewell | |
| 2009-02-10 | CPU: Prepare CPU models for the new in-order CPU model. | Korey Sewell | |
| Some new functions and forward declarations are necessary to make things work | |||
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