gem5 - gem5

Age	Commit message (Collapse)	Author
2010-03-21	ruby: Reordered protocol buffers	Brad Beckmann
	Reordered vnet priorities to agree with PerfectSwitch for protocols MI_example, MOESI_CMP_token, and MOESI_hammer
2010-03-21	ruby: Adds configurable bit selection for numa mapping	Brad Beckmann

2010-03-21	ruby: Added flag to disable mem_vec allocation	Brad Beckmann
	The RubySystem flag no_mem_vec will disable Ruby from allocating it's memory data array.
2010-03-21	ruby: Ruby support for sparse memory	Brad Beckmann
	The patch includes direct support for the MI example protocol.
2010-03-21	ruby: Finally removed bash code cira. 2001ish!	Brad Beckmann

2010-03-21	ruby: Ruby support for LLSC	Brad Beckmann

2010-03-21	ruby: Minor dma latency initialization fix	Brad Beckmann

2010-03-21	ruby: Fix multiple wakeups in Ruby Eventqueue	Tushar Krishna
	Fix bug in Ruby Event queue to avoid multiple wakeups of same consumer in same cycle
2010-03-21	ruby: Removed the obsolete file specified network files	Brad Beckmann

2010-03-21	ruby: Added copyright to many Ruby *.py files	Brad Beckmann

2010-03-21	ruby: Fixed small data msg bug in MOESI_hammer-dir	Brad Beckmann

2010-03-21	TimingSimpleCPU: Fixed uncacacheable request read bug	Brad Beckmann
	Previously the recording of an uncached read occurred after the request was possibly deleted within the translateTiming function.
2010-03-21	ruby: Removed the no longer used rubymem files	Brad Beckmann

2010-03-21	ruby: Fix MOESI_hammer cache profiler calls for L2 misses	Brad Beckmann

2010-03-21	ruby: Removed deprecated stats from the main profiler	Brad Beckmann

2010-03-16	orion: Make declarations match definition	Nathan Binkert

2010-03-14	ruby: Fix copyrights on files	Nathan Binkert
	Mostly files missed during import or screwed up during import
2010-03-12	slicc: Change the code generation so that the generated code is easier to read	Nathan Binkert

2010-03-12	packet: add a method to set the size	Nathan Binkert

2010-03-12	eventq: rearrange a little bit so I can add some stuff	Nathan Binkert

2010-03-12	eventq: remove some unused includes	Nathan Binkert

2010-03-12	bugfix: since pow() causes a bug don't use it	Nathan Binkert
	It's a power of two anyway, so why use it in the first place.
2010-03-10	ruby: get rid of std-includes.hh	Nathan Binkert
	Do not use "using namespace std;" in headers Include header files as needed
2010-03-10	ruby: remove calc_host.diff since we don't use it	Nathan Binkert

2010-03-10	ruby: get rid of the ioutil stuff since it isn't used anymore	Nathan Binkert

2010-03-10	slicc: have a central mechanism for creating a code_formatter.	Nathan Binkert
	This makes it easier to add global variables like protocol
2010-03-10	scons: import ply to work around scons sys.path weirdness	Nathan Binkert

2010-02-28	SmartDict: Make SmartDict an attrdict	Nathan Binkert

2010-02-28	uart: use integer versions of time instead of messing around with floats	Nathan Binkert

2010-02-26	cpu_models: get rid of cpu_models.py and move the stuff into SCons	Nathan Binkert

2010-02-26	isa_parser: Make SCons import the isa_parser	Nathan Binkert
	this is instead of forking a new interpreter
2010-02-26	isa_parser: move the operand map stuff into the ISAParser class.	Nathan Binkert

2010-02-26	isa_parser: move more support functions into the ISAParser class	Nathan Binkert

2010-02-26	isa_parser: move more stuff into the ISAParser class	Nathan Binkert

2010-02-26	isa_parser: move the formatMap and exportContext into the ISAParser class	Nathan Binkert

2010-02-26	isa_parser: Make stack objects class members instead of globals	Nathan Binkert

2010-02-26	isa_parser: add a debug variable that changes how errors are reported.	Nathan Binkert
	This allows us to get tracebacks in certain cases where they're more useful than our error message.
2010-02-26	isa_parser: Use an exception to flag error	Nathan Binkert
	This allows the error to propagate more easily
2010-02-26	isa_parser: Move more stuff into the ISAParser class	Nathan Binkert

2010-02-26	isa_parser: move code around to prepare for putting more stuff in the class	Nathan Binkert

2010-02-26	isa_parser: simple fixes, formatting and style	Nathan Binkert

2010-02-26	events: Give EventWrapped a default name and description	Nathan Binkert

2010-02-24	cache stats: account for writebacks and/or device occupancy in the cache.	Lisa Hsu
	Plus, a minor bugfix that neglects to update blk->contextSrc in certain cases on a cache insert.
2010-02-23	cache: Make caches sharing aware and add occupancy stats.	Lisa Hsu
	On the config end, if a shared L2 is created for the system, it is parameterized to have n sharers as defined by option.num_cpus. In addition to making the cache sharing aware so that discriminating tag policies can make use of context_ids to make decisions, I added an occupancy AverageStat and an occ % stat to each cache so that you could know which contexts are occupying how much cache on average, both in terms of blocks and percentage. Note that since devices have context_id -1, having an array of occ stats that correspond to each context_id will break here, so in FS mode I add an extra bucket for device blocks. This bucket is explicitly not added in SE mode in order to not only avoid ugliness in the stats.txt file, but to avoid broken stats (some formulas break when a bucket is 0).
2010-02-23	stats: this makes some fixes to AverageStat and AverageVector.	Lisa Hsu
	Also, make Formulas work on AverageVector. First, Stat::Average (and thus Stats::AverageVector) was broken when coming out of a checkpoint and on resets, this fixes that. Formulas also didn't work with AverageVector, but added support for that.
2010-02-23	cache: pull CacheSet out of LRU so that other tags can use associative sets.	Lisa Hsu

2010-02-20	BaseDynInst: Preserve the faults returned from read and write.	Timothy M. Jones
	When implementing timing address translations instead of atomic, I forgot to preserve the faults that are returned from the read and write calls. This patch reinstates them.
2010-02-12	O3PCU: Split loads and stores that cross cache line boundaries.	Timothy M. Jones
	When each load or store is sent to the LSQ, we check whether it will cross a cache line boundary and, if so, split it in two. This creates two TLB translations and two memory requests. Care has to be taken if the first packet of a split load is sent but the second blocks the cache. Similarly, for a store, if the first packet cannot be sent, we must store the second one somewhere to retry later. This modifies the LSQSenderState class to record both packets in a split load or store. Finally, a new const variable, HasUnalignedMemAcc, is added to each ISA to indicate whether unaligned memory accesses are allowed. This is used throughout the changed code so that compiler can optimise away code dealing with split requests for ISAs that don't need them.
2010-02-12	BaseDynInst: Make the TLB translation timing instead of atomic.	Timothy M. Jones
	This initiates a timing translation and passes the read or write on to the processor before waiting for it to finish. Once the translation is finished, the instruction's state is updated via the 'finish' function. A new DataTranslation class is created to handle this. The idea is taken from the implementation of timing translations in TimingSimpleCPU by Gabe Black. This patch also separates out the timing translations from this CPU and uses the new DataTranslation class.
2010-02-12	Power ISA: Add an alignment fault to Power ISA and check alignment in TLB.	Timothy M. Jones