| Age | Commit message (Expand) | Author |
|---|
| 2018-01-15 | arch: Fix a fatal_if in most of the arch's process classes. | Gabe Black |
| 2018-01-12 | sim: Allow passing a user-defined L2XBar to addTwoLevelCacheHierarchy(). | Xiaoyu Ma |
| 2018-01-11 | arch-riscv: Don't crash when printing unknown CSRs | Alec Roelke |
| 2018-01-11 | mem-ruby: Fix wakeup timeouts for the MOESI_CMP_token protocol | Nikos Nikoleris |
| 2018-01-11 | mem-ruby: Remove function that maps responses to a DMA engine | Nikos Nikoleris |
| 2018-01-11 | mem-ruby: Add support for multiple DMA engines in MESI_Two_Level | Nikos Nikoleris |
| 2018-01-11 | cpu: Make the CPU's TLB parameter a BaseTLB. | Gabe Black |
| 2018-01-11 | arm, power: Make the python TLB simobjects inherit from BaseTLB. | Gabe Black |
| 2018-01-11 | arch,mem: Remove the default value for page size. | Gabe Black |
| 2018-01-11 | arch,mem: Move page table construction into the arch classes. | Gabe Black |
| 2018-01-10 | style: change C/C++ source permissions to noexec | BKP |
| 2018-01-10 | arch-riscv: Make use of ImmOp's polymorphism | Alec Roelke |
| 2018-01-10 | alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT. | Gabe Black |
| 2018-01-10 | arch-riscv,sim: Support clone syscall in RISC-V | Tuan Ta |
| 2018-01-09 | mem-cache: Prune unnecessary writebacks in exclusive caches | Nikos Nikoleris |
| 2018-01-09 | cpu: Use the NotAnInst flag to avoid passing an inst to fetch faults. | Gabe Black |
| 2018-01-09 | cpu: Add a NotAnInst flag to the BaseDynInst class. | Gabe Black |
| 2018-01-09 | cpu, power: Get rid of the remnants of the EA computation insts. | Gabe Black |
| 2018-01-09 | arm: Make translateFunctional override the base implementation. | Gabe Black |
| 2018-01-05 | arch-riscv: Ignore sched_yield syscall in SE mode | Tuan Ta |
| 2018-01-05 | sim: Fix a bug in prlimit syscall in SE mode | Tuan Ta |
| 2018-01-05 | arch-riscv: Ignore set_robust_list and get_robust_list syscalls | Tuan Ta |
| 2018-01-05 | arch-riscv: Add an implementation of set_tid_address syscall in RISCV | Tuan Ta |
| 2018-01-05 | arch-riscv: Correct syscall argument reg count | Alec Roelke |
| 2018-01-04 | arch-riscv: Remove "magic" syscall number constant | Alec Roelke |
| 2017-12-23 | alpha,arm,mips,power,riscv,sparc,x86: Get rid of TheISA::NoopMachInst. | Gabe Black |
| 2017-12-23 | riscv,x86: Stop using the arch Nop machine instruction unnecessarily. | Gabe Black |
| 2017-12-22 | arch,cpu: "virtualize" the TLB interface. | Gabe Black |
| 2017-12-22 | cpu: Use the generic nop static inst instead of decoding the arch version. | Gabe Black |
| 2017-12-22 | cpu: Add a pointer to a generic Nop StaticInst. | Gabe Black |
| 2017-12-21 | arch-arm: Fixed WFE/WFI trapping behaviour | Giacomo Travaglini |
| 2017-12-21 | arch-arm: Hyp routed undef fault need to change its syndrome | Giacomo Travaglini |
| 2017-12-21 | arch-arm: Fix StaticInst encoding() method | Giacomo Travaglini |
| 2017-12-20 | cpu: Fix exit_gen.cc which used misc.hh instead of logging.hh. | Gabe Black |
| 2017-12-19 | arch-arm: Instruction size methods in StaticInst class | Giacomo Travaglini |
| 2017-12-19 | arch-arm: Change casting type from reinterpret to static | Giacomo Travaglini |
| 2017-12-19 | cpu-tester: Added ExitGen to TrafficGen | Riken Gohil |
| 2017-12-19 | cpu-tester: Refactoring traffic generators into separate files. | Riken Gohil |
| 2017-12-15 | mem-ruby: Support atomic_noncaching acceses in ruby | Swapnil Haria |
| 2017-12-14 | arch-riscv: Define AT_RANDOM properly | Alec Roelke |
| 2017-12-14 | arch-riscv: Increase maximum stack size | Alec Roelke |
| 2017-12-14 | misc: Updates for gcc7.2 for x86 | Jason Lowe-Power |
| 2017-12-14 | x86: Use operand size 4 when it would be 2 for cmpxchg8b. | Gabe Black |
| 2017-12-13 | scons, tests: Fix occasional linking error | Andreas Sandberg |
| 2017-12-13 | scons, tests: Add support for GTest XML generation | Andreas Sandberg |
| 2017-12-13 | scons: Make sure GTests have the right environment variables | Andreas Sandberg |
| 2017-12-13 | arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with. | Gabe Black |
| 2017-12-13 | cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst. | Gabe Black |
| 2017-12-13 | x86: Rework how "split" loads/stores are handled. | Gabe Black |
| 2017-12-13 | base: Add endianness conversion functions for std::array types. | Gabe Black |
