| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2010-12-20 | Style: Replace some tabs with spaces. | Gabe Black | |
| 2010-12-20 | Params: Fix a broken error message in verifyIp. | Gabe Black | |
| 2010-12-09 | ARM: Take advantage of new PCState syntax. | Gabe Black | |
| 2010-12-09 | ARM: Get rid of some unused FP operands. | Gabe Black | |
| 2010-12-08 | Merge. | Gabe Black | |
| 2010-12-08 | ruby: remove Ruby asserts for m5.fast | Brad Beckmann | |
| This diff is for changing the way ASSERT is handled in Ruby. m5.fast compiles out the assert statements by using the macro NDEBUG. Ruby uses the macro RUBY_NO_ASSERT to do so. This macro has been removed and NDEBUG has been put in its place. | |||
| 2010-12-08 | Alpha: Take advantage of new PCState syntax. | Gabe Black | |
| 2010-12-08 | MIPS: Take advantage of new PCState syntax. | Gabe Black | |
| 2010-12-08 | POWER: Take advantage of new PCState syntax. | Gabe Black | |
| 2010-12-08 | SPARC: Take advantage of new PCState syntax. | Gabe Black | |
| 2010-12-08 | X86: Take advantage of new PCState syntax. | Gabe Black | |
| 2010-12-07 | ISA: Get the parser to support pc state components more elegantly. | Gabe Black | |
| 2010-12-07 | O3: Allow a store entry to store up to 16 bytes (instead of TheISA::IntReg). | Ali Saidi | |
| The store queue doesn't need to be ISA specific and architectures can frequently store more than an int registers worth of data. A 128 bits seems more common, but even 256 bits may be appropriate. Pretty much anything less than a cache line size is buildable. | |||
| 2010-12-07 | O3: Support squashing all state after special instruction | Ali Saidi | |
| For SPARC ASIs are added to the ExtMachInst. If the ASI is changed simply marking the instruction as Serializing isn't enough beacuse that only stops rename. This provides a mechanism to squash all the instructions and refetch them | |||
| 2010-12-07 | O3: Make all instructions that write a misc. register not perform the write ↵ | Giacomo Gabrielli | |
| until commit. ARM instructions updating cumulative flags (ARM FP exceptions and saturation flags) are not serialized. Added aliases for ARM FP exceptions and saturation flags in FPSCR. Removed write accesses to the FP condition codes for most ARM VFP instructions: only VCMP and VCMPE instructions update the FP condition codes. Removed a potential cause of seg. faults in the O3 model for NEON memory macro-ops (ARM). | |||
| 2010-12-07 | O3: Support SWAP and predicated loads/store in ARM. | Min Kyu Jeong | |
| 2010-12-07 | ARM: Support switchover with hardware table walkers | Ali Saidi | |
| 2010-12-01 | ruby: Converted old ruby debug calls to M5 debug calls | Nilay Vaish | |
| This patch developed by Nilay Vaish converts all the old GEMS-style ruby debug calls to the appropriate M5 debug calls. | |||
| 2010-11-26 | IGbE: return 0 on an invalid descriptor size instead of -1. | Ali Saidi | |
| Asserts where descSize() get called with assert if we end up returning 0. | |||
| 2010-11-23 | Copyright: Add AMD copyright to the param changes I just made. | Gabe Black | |
| 2010-11-23 | Params: Add parameter types for IP addresses in various forms. | Gabe Black | |
| New parameter forms are: IP address in the format "a.b.c.d" where a-d are from decimal 0 to 255. IP address with netmask which is an IP followed by "/n" where n is a netmask length in bits from decimal 0 to 32 or by "/e.f.g.h" where e-h are from decimal 0 to 255 and which is all 1 bits followed by all 0 bits when represented in binary. These can also be specified as an integral IP and netmask passed in separately. IP address with port which is an IP followed by ":p" where p is a port index from decimal 0 to 65535. These can also be specified as an integral IP and port value passed in separately. | |||
| 2010-11-23 | X86: Loosen an assert for x86 and connect the APIC ports when caches are used. | Gabe Black | |
| 2010-11-23 | X86: Obey the PCD (cache disable) bit in the page tables. | Gabe Black | |
| 2010-11-22 | X86: Mark IO space accesses as uncachable. | Gabe Black | |
| 2010-11-22 | IDE,X86: Fix IDE controller BAR configuration for x86. | Gabe Black | |
| 2010-11-20 | random: small comment about our random number generator and its origin | Nathan Binkert | |
| 2010-11-19 | SE: Fix simulating more than 4GB of RAM in SE mode | Ali Saidi | |
| This change removes some dead code in PhysicalMemory, uses a 64 bit type for the page pointer in System (instead of 32 bit) and cleans up some style. | |||
| 2010-11-19 | SCons: Support building without an ISA | Ali Saidi | |
| 2010-11-18 | O3: Fix fp destination register flattening, and index offset adjusting. | Gabe Black | |
| This change makes O3 flatten floating point destination registers, and also fixes misc register flattening so that it's correctly repositioned relative to the resized regions for integer and floating point indices. It also fixes some overly long lines. | |||
| 2010-11-15 | O3: Make O3 support variably lengthed instructions. | Gabe Black | |
| 2010-11-15 | O3: reset architetural state by calling clear() | Ali Saidi | |
| 2010-11-15 | ARM: Add comment about the organization of the IT state register | Ali Saidi | |
| 2010-11-15 | CPU/ARM: Add SIMD op classes to CPU models and ARM ISA. | Giacomo Gabrielli | |
| 2010-11-15 | O3: prevent a squash when completeAcc() modifies misc reg through TC. | Min Kyu Jeong | |
| This happens on ARM instructions when they update the IT state bits. Code and associated comment was copied from execute() and initiateAcc() methods | |||
| 2010-11-15 | ARM: Return an FailUnimp instruction when an unimplemented CP15 register is ↵ | Ali Saidi | |
| accessed. Just panicing in readMiscReg() doesn't work because a speculative access in the o3 model can end the simulation. | |||
| 2010-11-15 | SCons: Cleanup SCons output during compile | Ali Saidi | |
| 2010-11-15 | ARM: Add a Keyboard Mouse Interface controller | William Wang | |
| 2010-11-15 | ARM: Implement a CLCD Frame buffer | William Wang | |
| 2010-11-15 | ARM: Add support for GDB on ARM | William Wang | |
| --HG-- rename : src/arch/alpha/remote_gdb.cc => src/arch/arm/remote_gdb.cc | |||
| 2010-11-15 | ARM: Make utility.hh meet style guidelines | Ali Saidi | |
| 2010-11-15 | ARM: Add support for a dumb IDE controller | Ali Saidi | |
| 2010-11-15 | ARM: Cache the misc regs at the TLB to limit readMiscReg() calls. | Ali Saidi | |
| 2010-11-15 | ARM: Add support for switching CPUs | Ali Saidi | |
| 2010-11-15 | ARM: Use the correct delete operator for RFE | Ali Saidi | |
| 2010-11-15 | ARM: Fix SRS instruction to micro-code memory operation and register update. | Ali Saidi | |
| Previously the SRS instruction attempted to writeback in initiateAcc() which worked until a recent change, but was incorrect. | |||
| 2010-11-15 | CPU: Fix bug when a split transaction is issued to a faster cache | Ali Saidi | |
| In the case of a split transaction and a cache that is faster than a CPU we could get two responses before next_tick expires. Add an event that is scheduled in this case and return false rather than asserting. | |||
| 2010-11-15 | ARM: Do something predictable for an UNPREDICTABLE branch. | Ali Saidi | |
| 2010-11-11 | Params: Fix an off by one error and a misleading comment. | Gabe Black | |
| 2010-11-11 | SimObject: Add a comment near clear_child that it's unlikely to be called. | Gabe Black | |
| 2010-11-11 | SPARC: Clean up some historical style issues. | Gabe Black | |
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