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AgeCommit message (Expand)Author
2012-09-25CPU: Add abandoned instructions to O3 Pipe ViewerDjordje Kovacevic
2012-09-25ARM: Inst writing to cntrlReg registers not set as control instNathanael Premillieu
2012-09-25ARM: Predict target of more instructions that modify PC.Ali Saidi
2012-09-25build: Add missing dependencies when building param SWIG interfacesAndreas Sandberg
2012-09-23RubyPort and Sequencer: Fix drainingJoel Hestness
2012-09-21DRAM: Introduce SimpleDRAM to capture a high-level controllerAndreas Hansson
2012-09-21TrafficGen: Add a basic traffic generatorAndreas Hansson
2012-09-21Mem: Tidy up bus member variables typesAndreas Hansson
2012-09-21SE: Ignore FUTEX_PRIVATE_FLAG of sys_futexLluc Alvarez
2012-09-20bus: removed outdated warn regarding 64 B block sizesAnthony Gutierrez
2012-09-19Mem: Remove the file parameter from AbstractMemoryAndreas Hansson
2012-09-19AddrRange: Transition from Range<T> to AddrRangeAndreas Hansson
2012-09-19AddrRange: Simplify Range by removing stream input/outputAndreas Hansson
2012-09-19AddrRange: Remove unused range_multimapAndreas Hansson
2012-09-19AddrRange: Simplify AddrRange params Python hierarchyAndreas Hansson
2012-09-18ruby: eliminate typedef integer_tNilay Vaish
2012-09-18ruby: avoid using g_system_ptr for event schedulingNilay Vaish
2012-09-18Mem: Add a maximum bandwidth to SimpleMemoryAndreas Hansson
2012-09-14gcc: Enable Link-Time Optimization for gcc >= 4.6Andreas Hansson
2012-09-14scons: Add a target for google-perftools profilingAndreas Hansson
2012-09-14scons: Restructure ccflags and ldflagsAndreas Hansson
2012-09-14scons: Use c++0x with gcc >= 4.4 instead of 4.6Andreas Hansson
2012-09-12Standard Switch: Drain the system before switching CPUsJoel Hestness
2012-09-12Base CPU: Initialize profileEvent to NULLJoel Hestness
2012-09-12Ruby: Modify Scons so that we can put .sm files in extrasJason Power
2012-09-12stats: remove duplicate instruction stats from the commit stageAnthony Gutierrez
2012-09-11clang: Fix issues identified by the clang static analyzerAndreas Hansson
2012-09-11Cache: Split invalidateBlk up to seperate block vs. tagsLena Olson
2012-09-11X86: make use of register predicationNilay Vaish
2012-09-11x86: Add a separate register for D flag bitNilay Vaish
2012-06-03ISA Parser: Allow predication of source and destination registersNilay Vaish
2012-09-11Ruby: Use uint32_t instead of uint32 everywhereNilay Vaish
2012-09-11Ruby: Use uint8_t instead of uint8 everywhereNilay Vaish
2012-09-10Ruby System: Convert to Clocked ObjectNilay Vaish
2012-09-10Ruby Slicc: remove the call to cin.get() functionNilay Vaish
2012-09-10Mem: Allow serializing of more than INT_MAX bytesMarco Elver
2012-09-10NetBSD: Build on NetBSDPalle Lyckegaard
2012-09-10AddrRange: Remove the unused range_ops headerAndreas Hansson
2012-09-10Inet: Remove the SackRange and its useAndreas Hansson
2012-09-10Device: Bump PIO and PCI latencies to more reasonable valuesAndreas Hansson
2012-09-07sim: Update the SimObject documentationAndreas Sandberg
2012-09-07sim: Remove the unused SimObject::regFormulas methodAndreas Sandberg
2012-09-07O3: Get rid of incorrect assert in RAS.Ali Saidi
2012-09-07dev: Fix bifield definition in timer_cpulocal.hhAli Saidi
2012-09-07Igbe: Newer kernels seem to allow TSO headers and packet data to be in one descAli Saidi
2012-09-07sim: add validation to make sure there is memory where we're loading the kernelKrishnendra Nathella
2012-09-07loader: initialize all memory in the ObjectFile objects.Ali Saidi
2012-09-07ARM: Fix one of the timers used in the VExpress EMM platform.Ali Saidi
2012-09-07Param: Transition to Cycles for relevant parametersAndreas Hansson
2012-09-05Ruby Memory Controller: Fix clockingJoel Hestness