summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Expand)Author
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-11-02cpu: O3 add a header declaring the DerivO3CPUAndreas Sandberg
2012-11-02cpu: Add header files for checker CPUsAndreas Sandberg
2012-11-02dev: Fix ethernet device inheritance structureAndreas Sandberg
2012-11-02sim: Include object header files in SWIG interfacesAndreas Sandberg
2012-11-02pci: Make Python wrapper cast to the right typeAndreas Sandberg
2012-11-02mips: Remove unused Python fileAndreas Sandberg
2012-11-02dev: Add missing inline declarationsAndreas Sandberg
2012-11-02base: Add missing header file to addr_range.hh.Andreas Sandberg
2012-11-02ARM: dump stats and process info on context switchesDam Sunwoo
2012-11-02base: Fix a few incorrectly handled print format casesChander Sudanthi
2012-11-02base: split out the VncServer into a VncInput and Server classesChander Sudanthi
2012-11-02ISA: generic Linux thread info supportDam Sunwoo
2012-11-02sim: Fix as issue where exit events on instr queues are used after freed.Ali Saidi
2012-11-02o3: Fix a couple of issues with the local predictor.Mrinmoy Ghosh
2012-11-02Partly revert [4f54b0f229b5] and move draining to m5.changeToTimingAndreas Sandberg
2012-10-31mem: Fix typo in port commentsAndreas Hansson
2012-10-25dev: Make default clock more reasonable for system and devicesAndreas Hansson
2012-10-25arm: Use table walker clock that is inherited from CPUAndreas Hansson
2012-10-23dev: Remove zero-time loop in DMA timing sendAndreas Hansson
2012-10-18ruby: functional access updates to network test protocolNilay Vaish
2012-10-15ruby: improved support for functional accessesNilay Vaish
2012-10-15memtest: move check on outstanding requestsNilay Vaish
2012-10-15 ruby: register multiple memory controllersNilay Vaish
2012-10-15ruby: remove AbstractMemOrCacheNilay Vaish
2012-10-15ruby: allow function definition in slicc structsNilay Vaish
2012-10-15ruby banked array: do away with event schedulingNilay Vaish
2012-10-15ruby: reset timing after cache warm upNilay Vaish
2012-10-15Mem: Fix incorrect logic in bus blocksize checkAndreas Hansson
2012-10-15Port: Add protocol-agnostic ports in the port hierarchyAndreas Hansson
2012-10-15Mem: Separate the host and guest views of memory backing storeAndreas Hansson
2012-10-15Checkpoint: Make system serialize call childrenAndreas Hansson
2012-10-15Mem: Use deque instead of list for bus retriesAndreas Hansson
2012-10-15Fix: Address a few minor issues identified by cppcheckAndreas Hansson
2012-10-15Mem: Use cycles to express cache-related latenciesAndreas Hansson
2012-10-15Regression: Use CPU clock and 32-byte width for L1-L2 busAndreas Hansson
2012-10-15Clock: Inherit the clock from parent by defaultAndreas Hansson
2012-10-15Param: Fix proxy traversal to support chained proxiesAndreas Hansson
2012-10-15Mem: Use range operations in bus in preparation for stripingAndreas Hansson
2012-10-11Mem: Determine bus block size during initialisationAndreas Hansson
2012-10-11Doxygen: Update the version of the DoxyfileAndreas Hansson
2012-10-02ruby: makes some members non-staticNilay Vaish
2012-10-02ruby: changes to simple networkNilay Vaish
2012-10-02ruby: rename template_hack to templateNilay Vaish
2012-10-02ruby: remove unused code in protocolsNilay Vaish
2012-10-02ruby: remove some unused things in sliccNilay Vaish
2012-10-02ruby: move functional access to ruby systemNilay Vaish
2012-09-30MI coherence protocol: add copyright noticeNilay Vaish
2012-09-25MEM: Put memory system document into doxygenDjordje Kovacevic
2012-09-25Cache: add a response latency to the cachesMrinmoy Ghosh