gem5 - gem5

Age	Commit message (Expand)	Author
2014-09-03	arm: Fix v8 neon latency issue for loads/stores	Mitch Hayenga
2014-04-29	arm: use condition code registers for ARM ISA	Curtis Dunham
2014-09-03	arm: ISA X31 destination register fix	Andrew Bardsley
2014-09-03	cpu: fix bimodal predictor to use correct global history reg	Dam Sunwoo
2014-09-03	arm: Mark v7 cbz instructions as direct branches	Mitch Hayenga
2014-09-03	cpu: Fix cache blocked load behavior in o3 cpu	Mitch Hayenga
2014-09-03	cpu: Fix o3 quiesce fetch bug	Mitch Hayenga
2014-09-03	cpu: Fix SMT scheduling issue with the O3 cpu	Mitch Hayenga
2014-09-03	cpu: Fix incorrect speculative branch predictor behavior	Mitch Hayenga
2014-09-03	cpu: Add a fetch queue to the o3 cpu	Mitch Hayenga
2014-09-03	cpu: Fix o3 front-end pipeline interlock behavior	Mitch Hayenga
2014-09-03	cpu: Change writeback modeling for outstanding instructions	Mitch Hayenga
2014-09-03	arch: Properly guess OpClass from optional StaticInst flags	Mitch Hayenga
2014-09-03	cache: Fix handling of LL/SC requests under contention	Geoffrey Blake
2014-05-27	arm: support 16kb vm granules	Curtis Dunham
2014-09-03	mem: Packet queue clean up	Andreas Hansson
2014-09-03	dev: Avoid invalid sized reads in PL390 with DPRINTF enabled	Mitch Hayenga
2014-09-03	sim: Fix checkpoint restore for Ticked	Andrew Bardsley
2014-09-03	arch, cpu: Factor out the ExecContext into a proper base class	Andreas Sandberg
2014-09-03	arch: Cleanup unused ISA traits constants	Andreas Hansson
2014-09-03	config: Change parsing of Addr so hex values work from scripts	Mitch Hayenga
2014-09-03	arm: Fix ExtMachInst hash operator underlying type	Andreas Hansson
2014-09-01	ruby: remove typedef of Index as int64	Nilay Vaish
2014-09-01	x86: set op class of two fp instructions	Nilay Vaish
2014-09-01	ruby: PerfectSwitch: moves code to a per vnet helper function	Nilay Vaish
2014-09-01	ruby: message buffers: significant changes	Nilay Vaish
2014-09-01	build opts: add MI_example to NULL ISA	Nilay Vaish
2014-09-01	mem: change the namespace Message to ProtoMessage	Nilay Vaish
2014-09-01	ruby: slicc: change the way configurable members are specified	Nilay Vaish
2014-09-01	ruby: slicc: improve the grammar	Nilay Vaish
2014-09-01	ruby: mesi three level: slight naming changes.	Nilay Vaish
2014-09-01	ruby: slicc: donot prefix machine name to variables	Nilay Vaish
2014-09-01	ruby: remove unused toString() from AbstractController	Nilay Vaish
2014-09-01	ruby: network: move getNumNodes() to base class	Nilay Vaish
2014-09-01	ruby: eliminate type Time	Nilay Vaish
2014-09-01	ruby: move files from ruby/system to ruby/structures	Nilay Vaish
2014-08-28	mem: adding architectural page table support for SE mode	Alexandru
2014-04-01	mem: adding a multi-level page table class	Alexandru
2014-08-26	mem: Fix DRAMSim2 cycle check when restoring from checkpoint	Andreas Hansson
2014-08-26	base: Add const to intmath and be more flexible with typing	Andreas Hansson
2014-08-26	base: Replace the internal varargs stuff with C++11 constructs	Andreas Sandberg
2014-08-26	base: Add compiler macros for C++11 final/override	Andreas Sandberg
2014-08-26	mips: Fix RLIMIT_RSS naming	Mitch Hayenga
2014-08-26	base: Add a static assert to check bit union ranges	Andreas Sandberg
2014-08-26	sparc: Fixup bit ordering in the PSTATE bit union	Andreas Sandberg
2014-08-26	mem: Update DRAM controller comments	Andreas Hansson
2014-08-26	mem: Fix address interleaving bug in DRAM controller	Andreas Hansson
2014-02-05	sim: bump checkpoint version for multiple event queues	Curtis Dunham
2014-08-13	arm: change MISCREG_L2ERRSR to warn not fail	Dam Sunwoo
2014-08-13	sim: remove kernel mapping check for baremetal workloads	Dam Sunwoo