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extra : convert_revision : 7e27b23b66c743b4625a1dd9d8d6ba61bff45168
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extra : convert_revision : 0be66513cb0cff07c0c2b50c97c1ea74d52b0dc9
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extra : convert_revision : 7bdf68f445b79b1b5dbcdfa5fa1005c68d03724c
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into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops
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extra : convert_revision : eed3b6a650635d43fe75c2158c8417647af640d9
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Rename cc_main to internal.main
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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extra : convert_revision : 498304c24435437f8f1942bb8aeafe69ba22a089
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check here for responses that match as well
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extra : convert_revision : 69c3628a381a9da885fab0272abf40c3411a5f0f
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Fixes for Mem Leak associated with Writebacks.
src/mem/cache/miss/mshr_queue.cc:
Fixes for Mem Leak associated with Writebacks. (Double Delete removed)
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extra : convert_revision : 7a52ddd57da35995896f2c4438a58aa53f762416
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If you get inserted in the front, reschedule the event
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extra : convert_revision : cfdd5b6911422fbb733677c43d027aa4407fbc85
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src/mem/cache/cache_impl.hh:
When upgrades change to readEx make sure to allocate the block
Fix dprintf
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extra : convert_revision : 8700a7e47ad042c8708302620b907849c4bfdded
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src/mem/cache/base_cache.cc:
On a delayed response, be sure to call the fixPacket wrapper to toggle hasData flag.
src/mem/packet.cc:
src/mem/packet.hh:
Create a wrapper to toggle the hasData flag on delayed responses
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extra : convert_revision : 1ced8d4e3dc12a059fb7636d59e429cd3dd46901
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extra : convert_revision : 4f5b610f364876b29ad0e04f1757e4b42d1f2bd8
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SConscript file instead of basing it on DEBUG
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extra : convert_revision : 6e6807cc4350ef92baeaaabfeb3dc0bb785128ba
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the parameters to the BaseCPU object.
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extra : convert_revision : 557292cffb40918133647b0c9ac653ee5112df2e
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extra : convert_revision : 863d395f8e7c8ee2aec708ffcef842317ec9a89b
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impression that this code is ISA independent.
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extra : convert_revision : 67d9e51702efbe5f5244268e3753328a6cf1a1d5
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src/arch/alpha/faults.hh:
Only use pagetable.hh in FS
src/arch/alpha/pagetable.hh:
pagetable.hh should only be included in FS, so protecting it internally should be unnecessary.
src/cpu/exetrace.cc:
Only use tlb.hh in FS
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extra : convert_revision : 91ea61f2e7970e7146b6d407ee250fcb20cd4d48
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to crash all configs.
Working on that now.
src/mem/cache/base_cache.cc:
Keep a list of the responders so we can search them on functional accesses.
src/mem/cache/base_cache.hh:
Properly put things on a list for responses so we can search the list.
Also, be sure to check the outgoing ports lists on a functional access (factor some common code out there)
src/mem/cache/cache_impl.hh:
Properly return when the first read hit on a functional access.
Make sure to call to check the other ports list of packets before forwarding it out.
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extra : convert_revision : 1d21cb55ff29c15716617efc48441329707c088a
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write intersections.
src/mem/packet.cc:
Make sure to copy the whole data (we were one byte short)
src/mem/tport.cc:
Fix for the proper semantics of fixPacket
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extra : convert_revision : 215e05db9099d427afd4994f5b29079354c847d8
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : e4f9bb663099662a94c5522e6b4955c2a83bac8d
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use memcpy instead of bcopy
s/u_int32_t/uint32_t/g
fixup endian code to work with solaris
hack to make sure htole() works... Nate, have a good idea to fix this?
src/arch/sparc/faults.cc:
set the reset address to be 40 bits. Makes PC printing easier at least for now.
src/arch/sparc/isa/base.isa:
fix endian issues with condition codes
src/arch/sparc/tlb.hh:
add implemented physical addres constants
src/arch/sparc/utility.hh:
add tlb.hh to utilities
src/base/loader/raw_object.cc:
add a symbol <filename>_start to the symbol table for binaries files
src/base/remote_gdb.cc:
use memcpy instead of bcopy
src/cpu/exetrace.cc:
clean up printing a bit more
src/cpu/m5legion_interface.h:
add tons to the shared interface
src/dev/ethertap.cc:
s/u_int32_t/uint32_t/g
src/dev/ide_atareg.h:
fixup endian code to work with solaris
src/dev/pcidev.cc:
src/sim/param.hh:
hack to make sure htole() works...
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extra : convert_revision : 4579392184b40bcc1062671a953c6595c685e9b2
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into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
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extra : convert_revision : 35e2ff6ce62281299ad98dca64ba04a3a8a6757c
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the virtual address.
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extra : convert_revision : 41478abc4d21d504420f6842338675c0767f7cf9
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Ctrl_Base_DepTag.
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properly.
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extra : convert_revision : f2cad8a5879999438ba9b05f15a91320e7a4cc4a
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code to read and write the strand_sts_reg, and made restored a Priv instruction.
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extra : convert_revision : 386512215f7243d230717c369217f8d2f9ada935
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extra : convert_revision : 38951352edbfc423fb6767a9aac49a703578c0ac
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into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
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extra : convert_revision : 0c2db1e1b5fdb91c1ac5705ab872a6bfb575a67a
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extra : convert_revision : 786735ecea8ff480db6b3754ac5daa562938d988
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constants.hh and isa_traits.cc
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called from the class's constructor.
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extra : convert_revision : 4e7a40ffe0a9a71fd1b2b171d9c0dcac50e1a1fe
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deterministic.
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extra : convert_revision : 38cd06f946fc0cc22288f71f567e77ce8fdfea99
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than sprintf which was breaking on 64 bit hosts.
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extra : convert_revision : 184d751392dfcc8c80ac1a6c0ebc3061ff0a3f20
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control register fields which won't work on a big endian host.
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extra : convert_revision : 1b518873b6e1a073b58cbe27642537d5ae3a604d
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specific DepTag constants.
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extra : convert_revision : e4af5e2fb2a6953f8837ad9bda309b7d6fa7abfb
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extra : convert_revision : d17d28a9520524e5f56bd79beb9b2be6ce76a22f
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bin files, cleanup lockstep printing a bit
Since we don't have a platform yet, you need to comment out the default responder stuff in Bus.py to make it work.
SConstruct:
Add TARGET_ISA to the list of environment variables that end up in the build_env for python
configs/common/FSConfig.py:
add a simple SPARC system to being testing with, you'll need to change makeLinuxAlphaSystem to makeSparcSystem in fs.py for now
src/SConscript:
add a raw file object, at least until we get more info about how to compile openboot properly
src/arch/sparc/system.cc:
src/arch/sparc/system.hh:
add parameters for ROM files (OBP/Reset/Hypervisor), a ROM, load files into ROM
src/base/loader/object_file.cc:
src/base/loader/object_file.hh:
add option to try raw when nothing works
src/cpu/exetrace.cc:
cleanup lockstep printing a little bit
src/cpu/m5legion_interface.h:
change the instruction to be 32 bits because it is
src/mem/physical.cc:
fix assert that doesn't work if memory starts somewhere above 0
src/python/m5/objects/BaseCPU.py:
Add if statement to choose between sparc tlbs and alpha tlbs
src/python/m5/objects/System.py:
Add a sparc system that sets the rom addresses correctly
src/python/m5/params.py:
add the ability to add Addr() together
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extra : convert_revision : bbbd8a56134f2dda2728091f740e2f7119b0c4af
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files so the directories can easily be deleted.
Remove the FullCPU from the ALL_CPU_LIST and only add it if
it exists.
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extra : convert_revision : b16f56bb92a0063803c5099732dc289fe4363768
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into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops
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extra : convert_revision : dc165840841bdd88e40111b98d1be493441703f0
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extra : convert_revision : 86f5585fe9ceb2ee30836d35384ebcddc1357c2a
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extra : convert_revision : 10c50c2d45a8e510d71cccde520059363116da8a
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into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
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extra : convert_revision : 5f4b39beba9f672ba1741cb45f4c3cf853ce574b
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : 643e28482e6739bd264a9c2d69c17279853aa0c5
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