gem5 - gem5

Age	Commit message (Expand)	Author
2014-05-09	mem: Add DRAM cycle time	Andreas Hansson
2014-05-09	mem: Simplify DRAM response scheduling	Andreas Hansson
2014-05-09	mem: Add precharge all (PREA) to the DRAM controller	Andreas Hansson
2014-05-09	mem: Remove printing of DRAM params	Andreas Hansson
2014-05-09	mem: Add tRTP to the DRAM controller	Andreas Hansson
2014-05-09	mem: Merge DRAM latency calculation and bank state update	Andreas Hansson
2014-05-09	mem: Add tWR to DRAM activate and precharge constraints	Andreas Hansson
2014-05-09	mem: Merge DRAM page-management calculations	Andreas Hansson
2014-05-09	mem: Add DRAM power states to the controller	Andreas Hansson
2014-05-09	mem: Ensure DRAM refresh respects timings	Andreas Hansson
2014-05-09	mem: Make DRAM read/write switching less conservative	Andreas Hansson
2014-04-17	arm: Make sure UndefinedInstructions are properly initialized	Ali Saidi
2014-04-17	arm: allow DC instructions by default so SE mode works	Ali Saidi
2014-04-17	sim, arm: implement more of the at variety syscalls	Ali Saidi
2014-05-09	cpu: Useful getters for ActivityRecorder	Andrew Bardsley
2014-05-09	cpu: Add flag name printing to StaticInst	Andrew Bardsley
2014-05-09	cpu: Timebuf const accessors	Andrew Bardsley
2014-05-09	arm: Add branch flags onto macroops	Andrew Bardsley
2014-05-09	cpu: Allow setWhen on trace objects	Andrew Bardsley
2014-05-09	arm: add preliminary ISA splits for ARM arch	Curtis Dunham
2014-05-09	arch: teach ISA parser how to split code across files	Curtis Dunham
2014-05-09	config: Avoid generating a reference to myself for Parent.any	Geoffrey Blake
2014-05-09	arch, arm: Preserve TLB bootUncacheability when switching CPUs	Geoffrey Blake
2014-05-09	cpu: add more instruction mix statistics	Curtis Dunham
2014-05-09	mem: Squash prefetch requests from downstream caches	Mitch Hayenga
2014-05-09	stats: Method stats source	Stephan Diestelhorst
2014-05-09	cpu, arm: Allow the specification of a socket field	Akash Bagdia
2014-05-09	mem: Auto-generate CommMonitor trace file names	Sascha Bischoff
2014-05-09	arm: Panics in miscreg read functions can be tripped by O3 model	Geoffrey Blake
2014-05-09	dev: Set HDLCD default pixel clock for 1080p @ 60Hz	Chris Emmons
2014-05-09	arm: quick hack to allow a greater number of CPUs to a guest OS	Matt Evans
2014-05-09	arch: remove inline specifiers on all inst constrs, all ISAs	Curtis Dunham
2014-05-09	arm: cleanup ARM ISA definition	Curtis Dunham
2014-05-09	scons: Require SWIG >= 2.0.4 and remove vector typemaps	Curtis Dunham
2014-04-23	arm: Correctly display disassembly of vldmia/vstmia	Curtis Dunham
2014-04-23	sim: Use correct unit for abort message	Andreas Hansson
2014-04-23	cpu: Fix setTranslateLatency() bug for squashed instructions	Mitchell Hayenga
2014-04-23	misc: Proper type check and import for PortRef	Sascha Bischoff
2014-04-01	cpu: Fix case where o3 lsq could print out uninitialized data	Mitch Hayenga
2014-04-01	mem: Don't print out the data of a cache block	Mitch Hayenga
2014-04-23	arm: Don't use a stack allocated mnemonic	Mitchell Hayenga
2014-04-23	cpu: Add O3 CPU width checks	Dam Sunwoo
2014-04-23	base: explicitly suggest potential use of 'All' debug flags	Curtis Dunham
2014-04-23	arch: remove 'null update' check in isa-parser	Curtis Dunham
2014-02-10	stats: better error message for uninitialized statistic	Curtis Dunham
2014-04-19	ruby: slicc: remove old documentation	Nilay Vaish
2014-04-19	ruby: slicc: slight change to rule for transitions	Nilay Vaish
2014-04-19	o3: Fix occupancy checks for SMT	Faissal Sleiman
2014-04-19	ruby: recorder: Fix (de-)serializing with different cache block-sizes	Marco Elver
2014-04-09	kvm, x86: Add initial support for multicore simulation	Andreas Sandberg