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AgeCommit message (Expand)Author
2007-01-03set __name__ in the root m5 script to __m5_main__ so we canNathan Binkert
2007-01-03FormattingNathan Binkert
2007-01-03Add 'Time' as a parameter type that can accept variousNathan Binkert
2006-12-30Fix up previous commit to proper logic.Kevin Lim
2006-12-29Merge zizzer.eecs.umich.edu:/bk/newmemNathan Binkert
2006-12-29FormattingNathan Binkert
2006-12-27Merge zizzer:/bk/newmemAli Saidi
2006-12-27Bug fixes in the TLBAli Saidi
2006-12-27Compare legion and m5 tlbs for differencesAli Saidi
2006-12-27Change MemoryAccess dprintfs to print the data as wellAli Saidi
2006-12-27No need to use NULL, just use 0Nathan Binkert
2006-12-26Remove some #if FULL_SYSTEMs so MP stuff works even in SE mode.Kevin Lim
2006-12-24Make sure that all of the bits in the result are setNathan Binkert
2006-12-24remove some output formatting stuff that we don't useNathan Binkert
2006-12-21Fix copyrightNathan Binkert
2006-12-21Expose the C++ event queue to python via the python functionNathan Binkert
2006-12-21styleNathan Binkert
2006-12-21Create a wrapper function to more easily add swig stuff to the buildNathan Binkert
2006-12-21move the swig initialization calls from src/sim/main.cc toNathan Binkert
2006-12-20don't use (*activeThreads).begin(), use activeThreads->blah().Nathan Binkert
2006-12-20Merge zizzer.eecs.umich.edu:/bk/newmemNathan Binkert
2006-12-20<scold> Make sure that variables are always initalized! </scold>Nathan Binkert
2006-12-19Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemSteve Reinhardt
2006-12-19Merge zizzer:/bk/newmemAli Saidi
2006-12-19fix twinx loads a little bitAli Saidi
2006-12-18Streamline Cache/Tags interface: get rid of redundant functions,Steve Reinhardt
2006-12-18No need to template prefetcher on cache TagStore type.Steve Reinhardt
2006-12-18Get rid of generic CacheTags object (fold back into Cache).Steve Reinhardt
2006-12-18Fix unittest compilesNathan Binkert
2006-12-18cast chars to int when we want to print integers so we get a numberNathan Binkert
2006-12-18move the twinx loads to the correct opcode and add asis 0x24 and 0x27Ali Saidi
2006-12-17Compilation fixes.Gabe Black
2006-12-17Added in the extended twin load formatGabe Black
2006-12-16Merge zizzer:/bk/newmemGabe Black
2006-12-16Merge zizzer:/bk/sparcfs/Gabe Black
2006-12-16Support for twin loads.Gabe Black
2006-12-16Compiler error fix.Gabe Black
2006-12-15Merge zizzer:/bk/newmemLisa Hsu
2006-12-15small change to eliminate address range overlap.Lisa Hsu
2006-12-15little fixes i noticed while searching for reason for address range issues (b...Lisa Hsu
2006-12-15Merge zizzer:/bk/sparcfsLisa Hsu
2006-12-15some small general fixes to make everythign work nicely with other ISAs, now ...Lisa Hsu
2006-12-15tlb.cc:Lisa Hsu
2006-12-15Use my range_map to speed up findPort() in the bus. The snoop code could stil...Ali Saidi
2006-12-15Optimized the TLB translations with some cachingAli Saidi
2006-12-14flesh out twinx asisAli Saidi
2006-12-13Split CachePort class into CpuSidePort and MemSidePortSteve Reinhardt
2006-12-13Merge zizzer:/bk/newmemLisa Hsu
2006-12-13fix MiscRegFile::readRegWithEffect, which neglected the MISCREGS.Lisa Hsu
2006-12-13Merge zizzer:/bk/newmemLisa Hsu
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